📄 piso.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register add:s4\|stand\[3\] memory sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg3 79.88 MHz 12.518 ns Internal " "Info: Clock clk has Internal fmax of 79.88 MHz between source register add:s4\|stand\[3\] and destination memory sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg3 (period= 12.518 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.851 ns + Longest register memory " "Info: + Longest register to memory delay is 1.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add:s4\|stand\[3\] 1 REG LC_X15_Y7_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N2; Fanout = 1; REG Node = 'add:s4\|stand\[3\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { add:s4|stand[3] } "NODE_NAME" } } } { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.468 ns) + CELL(0.383 ns) 1.851 ns sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg3 2 MEM M4K_X13_Y8 8 " "Info: 2: + IC(1.468 ns) + CELL(0.383 ns) = 1.851 ns; Loc. = M4K_X13_Y8; Fanout = 8; MEM Node = 'sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg3'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.851 ns" { add:s4|stand[3] sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 281 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns 20.69 % " "Info: Total cell delay = 0.383 ns ( 20.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.468 ns 79.31 % " "Info: Total interconnect delay = 1.468 ns ( 79.31 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.851 ns" { add:s4|stand[3] sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.091 ns - Smallest " "Info: - Smallest clock skew is -4.091 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.770 ns + Shortest memory " "Info: + Shortest clock path from clock clk to destination memory is 2.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 85; CLK Node = 'clk'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.722 ns) 2.770 ns sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg3 2 MEM M4K_X13_Y8 8 " "Info: 2: + IC(0.579 ns) + CELL(0.722 ns) = 2.770 ns; Loc. = M4K_X13_Y8; Fanout = 8; MEM Node = 'sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg3'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.301 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 281 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.10 % " "Info: Total cell delay = 2.191 ns ( 79.10 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.90 % " "Info: Total interconnect delay = 0.579 ns ( 20.90 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.770 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.861 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 6.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 85; CLK Node = 'clk'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.935 ns) 2.941 ns pf:s1\|flag 2 REG LC_X8_Y6_N6 52 " "Info: 2: + IC(0.537 ns) + CELL(0.935 ns) = 2.941 ns; Loc. = LC_X8_Y6_N6; Fanout = 52; REG Node = 'pf:s1\|flag'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.472 ns" { clk pf:s1|flag } "NODE_NAME" } } } { "G:/EDA/piso/pf.vhd" "" "" { Text "G:/EDA/piso/pf.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.209 ns) + CELL(0.711 ns) 6.861 ns add:s4\|stand\[3\] 3 REG LC_X15_Y7_N2 1 " "Info: 3: + IC(3.209 ns) + CELL(0.711 ns) = 6.861 ns; Loc. = LC_X15_Y7_N2; Fanout = 1; REG Node = 'add:s4\|stand\[3\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "3.920 ns" { pf:s1|flag add:s4|stand[3] } "NODE_NAME" } } } { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 45.40 % " "Info: Total cell delay = 3.115 ns ( 45.40 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.746 ns 54.60 % " "Info: Total interconnect delay = 3.746 ns ( 54.60 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "6.861 ns" { clk pf:s1|flag add:s4|stand[3] } "NODE_NAME" } } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.770 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "6.861 ns" { clk pf:s1|flag add:s4|stand[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" { } { { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 281 2 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 8 -1 0 } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 281 2 0 } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.851 ns" { add:s4|stand[3] sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.770 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "6.861 ns" { clk pf:s1|flag add:s4|stand[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|HUB_TDO~reg0 107.25 MHz 9.324 ns Internal " "Info: Clock altera_internal_jtag~TCKUTAP has Internal fmax of 107.25 MHz between source register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] and destination register sld_hub:sld_hub_inst\|HUB_TDO~reg0 (period= 9.324 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.401 ns + Longest register register " "Info: + Longest register to register delay is 4.401 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LC_X21_Y11_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.442 ns) 1.636 ns sld_hub:sld_hub_inst\|HUB_TDO~578 2 COMB LC_X21_Y12_N2 1 " "Info: 2: + IC(1.194 ns) + CELL(0.442 ns) = 1.636 ns; Loc. = LC_X21_Y12_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~578'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.636 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~578 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.457 ns) + CELL(0.114 ns) 3.207 ns sld_hub:sld_hub_inst\|HUB_TDO~579 3 COMB LC_X16_Y12_N6 1 " "Info: 3: + IC(1.457 ns) + CELL(0.114 ns) = 3.207 ns; Loc. = LC_X16_Y12_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~579'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.571 ns" { sld_hub:sld_hub_inst|HUB_TDO~578 sld_hub:sld_hub_inst|HUB_TDO~579 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.738 ns) 4.401 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 4 REG LC_X16_Y12_N3 0 " "Info: 4: + IC(0.456 ns) + CELL(0.738 ns) = 4.401 ns; Loc. = LC_X16_Y12_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.194 ns" { sld_hub:sld_hub_inst|HUB_TDO~579 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.294 ns 29.40 % " "Info: Total cell delay = 1.294 ns ( 29.40 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.107 ns 70.60 % " "Info: Total interconnect delay = 3.107 ns ( 70.60 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.401 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~578 sld_hub:sld_hub_inst|HUB_TDO~579 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.890 ns + Shortest register " "Info: + Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 205 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 205; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.179 ns) + CELL(0.711 ns) 4.890 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X16_Y12_N3 0 " "Info: 2: + IC(4.179 ns) + CELL(0.711 ns) = 4.890 ns; Loc. = LC_X16_Y12_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.54 % " "Info: Total cell delay = 0.711 ns ( 14.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.179 ns 85.46 % " "Info: Total interconnect delay = 4.179 ns ( 85.46 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.890 ns - Longest register " "Info: - Longest clock path from clock altera_internal_jtag~TCKUTAP to source register is 4.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 205 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 205; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.179 ns) + CELL(0.711 ns) 4.890 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 2 REG LC_X21_Y11_N8 1 " "Info: 2: + IC(4.179 ns) + CELL(0.711 ns) = 4.890 ns; Loc. = LC_X21_Y11_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.54 % " "Info: Total cell delay = 0.711 ns ( 14.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.179 ns 85.46 % " "Info: Total interconnect delay = 4.179 ns ( 85.46 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.401 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~578 sld_hub:sld_hub_inst|HUB_TDO~579 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.890 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "load " "Info: No valid register-to-register paths exist for clock load" { } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sck register piso:s2\|lpm_counter:i_rtl_0\|cntr_fa7:auto_generated\|safe_q\[1\] register piso:s2\|po\[1\] 195.43 MHz 5.117 ns Internal " "Info: Clock sck has Internal fmax of 195.43 MHz between source register piso:s2\|lpm_counter:i_rtl_0\|cntr_fa7:auto_generated\|safe_q\[1\] and destination register piso:s2\|po\[1\] (period= 5.117 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.894 ns + Longest register register " "Info: + Longest register to register delay is 4.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns piso:s2\|lpm_counter:i_rtl_0\|cntr_fa7:auto_generated\|safe_q\[1\] 1 REG LC_X19_Y5_N6 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y5_N6; Fanout = 19; REG Node = 'piso:s2\|lpm_counter:i_rtl_0\|cntr_fa7:auto_generated\|safe_q\[1\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "F:/EDA/piso/db/cntr_fa7.tdf" "" "" { Text "F:/EDA/piso/db/cntr_fa7.tdf" 84 8 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.111 ns) + CELL(0.442 ns) 2.553 ns piso:s2\|Decoder~34 2 COMB LC_X16_Y6_N6 1 " "Info: 2: + IC(2.111 ns) + CELL(0.442 ns) = 2.553 ns; Loc. = LC_X16_Y6_N6; Fanout = 1; COMB Node = 'piso:s2\|Decoder~34'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.553 ns" { piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] piso:s2|Decoder~34 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 3.571 ns piso:s2\|po\[1\]~49 3 COMB LC_X16_Y6_N7 1 " "Info: 3: + IC(0.428 ns) + CELL(0.590 ns) = 3.571 ns; Loc. = LC_X16_Y6_N7; Fanout = 1; COMB Node = 'piso:s2\|po\[1\]~49'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.018 ns" { piso:s2|Decoder~34 piso:s2|po[1]~49 } "NODE_NAME" } } } { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.867 ns) 4.894 ns piso:s2\|po\[1\] 4 REG LC_X16_Y6_N3 2 " "Info: 4: + IC(0.456 ns) + CELL(0.867 ns) = 4.894 ns; Loc. = LC_X16_Y6_N3; Fanout = 2; REG Node = 'piso:s2\|po\[1\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.323 ns" { piso:s2|po[1]~49 piso:s2|po[1] } "NODE_NAME" } } } { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns 38.80 % " "Info: Total cell delay = 1.899 ns ( 38.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.995 ns 61.20 % " "Info: Total interconnect delay = 2.995 ns ( 61.20 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.894 ns" { piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] piso:s2|Decoder~34 piso:s2|po[1]~49 piso:s2|po[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.038 ns - Smallest " "Info: - Smallest clock skew is 0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck destination 2.759 ns + Shortest register " "Info: + Shortest clock path from clock sck to destination register is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sck 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'sck'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { sck } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.711 ns) 2.759 ns piso:s2\|po\[1\] 2 REG LC_X16_Y6_N3 2 " "Info: 2: + IC(0.579 ns) + CELL(0.711 ns) = 2.759 ns; Loc. = LC_X16_Y6_N3; Fanout = 2; REG Node = 'piso:s2\|po\[1\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.290 ns" { sck piso:s2|po[1] } "NODE_NAME" } } } { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.01 % " "Info: Total cell delay = 2.180 ns ( 79.01 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.99 % " "Info: Total interconnect delay = 0.579 ns ( 20.99 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.759 ns" { sck piso:s2|po[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck source 2.721 ns - Longest register " "Info: - Longest clock path from clock sck to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sck 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'sck'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { sck } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns piso:s2\|lpm_counter:i_rtl_0\|cntr_fa7:auto_generated\|safe_q\[1\] 2 REG LC_X19_Y5_N6 19 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X19_Y5_N6; Fanout = 19; REG Node = 'piso:s2\|lpm_counter:i_rtl_0\|cntr_fa7:auto_generated\|safe_q\[1\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.252 ns" { sck piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "F:/EDA/piso/db/cntr_fa7.tdf" "" "" { Text "F:/EDA/piso/db/cntr_fa7.tdf" 84 8 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.721 ns" { sck piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] } "NODE_NAME" } } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.759 ns" { sck piso:s2|po[1] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.721 ns" { sck piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "F:/EDA/piso/db/cntr_fa7.tdf" "" "" { Text "F:/EDA/piso/db/cntr_fa7.tdf" 84 8 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.894 ns" { piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] piso:s2|Decoder~34 piso:s2|po[1]~49 piso:s2|po[1] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.759 ns" { sck piso:s2|po[1] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.721 ns" { sck piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "piso:s2\|po\[14\] load sck 7.826 ns register " "Info: tsu for register piso:s2\|po\[14\] (data pin = load, clock pin = sck) is 7.826 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.548 ns + Longest pin register " "Info: + Longest pin to register delay is 10.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns load 1 CLK PIN_77 49 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_77; Fanout = 49; CLK Node = 'load'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { load } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.525 ns) + CELL(0.442 ns) 8.436 ns piso:s2\|po\[14\]~36 2 COMB LC_X19_Y5_N3 1 " "Info: 2: + IC(6.525 ns) + CELL(0.442 ns) = 8.436 ns; Loc. = LC_X19_Y5_N3; Fanout = 1; COMB Node = 'piso:s2\|po\[14\]~36'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "6.967 ns" { load piso:s2|po[14]~36 } "NODE_NAME" } } } { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.867 ns) 10.548 ns piso:s2\|po\[14\] 3 REG LC_X20_Y6_N4 1 " "Info: 3: + IC(1.245 ns) + CELL(0.867 ns) = 10.548 ns; Loc. = LC_X20_Y6_N4; Fanout = 1; REG Node = 'piso:s2\|po\[14\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.112 ns" { piso:s2|po[14]~36 piso:s2|po[14] } "NODE_NAME" } } } { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns 26.34 % " "Info: Total cell delay = 2.778 ns ( 26.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.770 ns 73.66 % " "Info: Total interconnect delay = 7.770 ns ( 73.66 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "10.548 ns" { load piso:s2|po[14]~36 piso:s2|po[14] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck destination 2.759 ns - Shortest register " "Info: - Shortest clock path from clock sck to destination register is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sck 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'sck'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { sck } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.711 ns) 2.759 ns piso:s2\|po\[14\] 2 REG LC_X20_Y6_N4 1 " "Info: 2: + IC(0.579 ns) + CELL(0.711 ns) = 2.759 ns; Loc. = LC_X20_Y6_N4; Fanout = 1; REG Node = 'piso:s2\|po\[14\]'" { } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.290 ns" { sck piso:s2|po[14] } "NODE_NAME" } } } { "F:/EDA/piso/piso.vhd" "" "" { Text "F:/EDA/piso/piso.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.01 % " "Info: Total cell delay = 2.180 ns ( 79.01 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.99 % " "Info: Total interconnect delay = 0.579 ns ( 20.99 % )" { } { } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.759 ns" { sck piso:s2|po[14] } "NODE_NAME" } } } } 0} } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "10.548 ns" { load piso:s2|po[14]~36 piso:s2|po[14] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.759 ns" { sck piso:s2|po[14] } "NODE_NAME" } } } } 0}
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