piso.fit.qmsg

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "1 " "Info: Fitter placement preparation operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.570 ns register memory " "Info: Estimated most critical path is register to memory delay of 1.570 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add:s4\|stand\[0\] 1 REG LAB_X15_Y8 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y8; Fanout = 8; REG Node = 'add:s4\|stand\[0\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { add:s4|stand[0] } "NODE_NAME" } } } { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.383 ns) 1.570 ns sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg0 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(1.187 ns) + CELL(0.383 ns) = 1.570 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|ram_block3a7~porta_address_reg0'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.570 ns" { add:s4|stand[0] sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 281 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns 24.39 % " "Info: Total cell delay = 0.383 ns ( 24.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.187 ns 75.61 % " "Info: Total interconnect delay = 1.187 ns ( 75.61 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.570 ns" { add:s4|stand[0] sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Info: Estimated interconnect usage is 6% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "2 " "Info: Fitter placement operations ending: elapsed time = 2 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[8\] GND " "Info: Pin st\[8\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[8\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[8] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[7\] GND " "Info: Pin st\[7\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[7\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[7] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[6\] GND " "Info: Pin st\[6\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[6\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[6] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[5\] GND " "Info: Pin st\[5\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[5\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[5] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[4\] GND " "Info: Pin st\[4\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[4\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[4] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[3\] GND " "Info: Pin st\[3\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[3\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[3] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[2\] GND " "Info: Pin st\[2\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[2\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[2] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[1\] GND " "Info: Pin st\[1\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[1\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[1] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "st\[0\] GND " "Info: Pin st\[0\] has GND driving its datain port" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "st\[0\]" } } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { st[0] } "NODE_NAME" } } } { "G:/EDA/piso/piso.fld" "" "" { Floorplan "G:/EDA/piso/piso.fld" "" "" { st[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 21:18:45 2005 " "Info: Processing ended: Sun Aug 28 21:18:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0}  } {  } 0}