piso.hier_info

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

address_b[8] => ram_block3a3.PORTBADDR8
address_b[8] => ram_block3a4.PORTBADDR8
address_b[8] => ram_block3a5.PORTBADDR8
address_b[8] => ram_block3a6.PORTBADDR8
address_b[8] => ram_block3a7.PORTBADDR8
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE


|top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
address[8] <= ram_rom_addr_reg[8].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= ram_rom_incr_addr~1.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~15.DATAB
data_read[1] => ram_rom_data_reg~14.DATAB
data_read[2] => ram_rom_data_reg~13.DATAB
data_read[3] => ram_rom_data_reg~12.DATAB
data_read[4] => ram_rom_data_reg~11.DATAB
data_read[5] => ram_rom_data_reg~10.DATAB
data_read[6] => ram_rom_data_reg~9.DATAB
data_read[7] => ram_rom_data_reg~8.DATAB
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[6].CLK
raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ram_rom_incr_write_addr_reg.CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => is_in_use_reg.CLK
raw_tck => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.TCK
raw_tck => ram_rom_addr_reg[8].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~0.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN0
usr1 => no_name_gen~0.IN0
jtag_state_cdr => no_name_gen~1.IN1
jtag_state_sdr => sdr.IN0
jtag_state_sdr => no_name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => e1dr.IN1
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN1
ena => no_name_gen~0.IN1
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => ir_loaded_address_reg[3].ACLR
ir_in[0] => ir_loaded_address_reg[2].ACLR
ir_in[0] => ir_loaded_address_reg[1].ACLR
ir_in[0] => ir_loaded_address_reg[0].ACLR
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[8].ACLR
ir_in[1] => process1~0.IN1
ir_in[1] => process1~2.IN0
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~0.IN0
ir_in[2] => ram_rom_incr_addr~1.IN1
ir_in[3] => process0~0.IN1
ir_in[3] => process1~3.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process5~0.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
ROM_DATA[0] => Mux~0.IN69
ROM_DATA[0] => Mux~1.IN69
ROM_DATA[0] => Mux~2.IN69
ROM_DATA[0] => Mux~3.IN69
ROM_DATA[1] => Mux~0.IN68
ROM_DATA[1] => Mux~1.IN68
ROM_DATA[1] => Mux~2.IN68
ROM_DATA[1] => Mux~3.IN68
ROM_DATA[2] => Mux~0.IN67
ROM_DATA[2] => Mux~1.IN67
ROM_DATA[2] => Mux~2.IN67
ROM_DATA[2] => Mux~3.IN67
ROM_DATA[3] => Mux~0.IN66
ROM_DATA[3] => Mux~1.IN66
ROM_DATA[3] => Mux~2.IN66
ROM_DATA[3] => Mux~3.IN66
ROM_DATA[4] => Mux~0.IN65
ROM_DATA[4] => Mux~1.IN65
ROM_DATA[4] => Mux~2.IN65
ROM_DATA[4] => Mux~3.IN65
ROM_DATA[5] => Mux~0.IN64
ROM_DATA[5] => Mux~1.IN64
ROM_DATA[5] => Mux~2.IN64
ROM_DATA[5] => Mux~3.IN64
ROM_DATA[6] => Mux~0.IN63
ROM_DATA[6] => Mux~1.IN63
ROM_DATA[6] => Mux~2.IN63
ROM_DATA[6] => Mux~3.IN63
ROM_DATA[7] => Mux~0.IN62
ROM_DATA[7] => Mux~1.IN62
ROM_DATA[7] => Mux~2.IN62
ROM_DATA[7] => Mux~3.IN62
ROM_DATA[8] => Mux~0.IN61
ROM_DATA[8] => Mux~1.IN61
ROM_DATA[8] => Mux~2.IN61
ROM_DATA[8] => Mux~3.IN61
ROM_DATA[9] => Mux~0.IN60
ROM_DATA[9] => Mux~1.IN60
ROM_DATA[9] => Mux~2.IN60
ROM_DATA[9] => Mux~3.IN60
ROM_DATA[10] => Mux~0.IN59
ROM_DATA[10] => Mux~1.IN59
ROM_DATA[10] => Mux~2.IN59
ROM_DATA[10] => Mux~3.IN59
ROM_DATA[11] => Mux~0.IN58
ROM_DATA[11] => Mux~1.IN58
ROM_DATA[11] => Mux~2.IN58
ROM_DATA[11] => Mux~3.IN58
ROM_DATA[12] => Mux~0.IN57
ROM_DATA[12] => Mux~1.IN57
ROM_DATA[12] => Mux~2.IN57
ROM_DATA[12] => Mux~3.IN57
ROM_DATA[13] => Mux~0.IN56
ROM_DATA[13] => Mux~1.IN56
ROM_DATA[13] => Mux~2.IN56
ROM_DATA[13] => Mux~3.IN56
ROM_DATA[14] => Mux~0.IN55
ROM_DATA[14] => Mux~1.IN55
ROM_DATA[14] => Mux~2.IN55
ROM_DATA[14] => Mux~3.IN55
ROM_DATA[15] => Mux~0.IN54
ROM_DATA[15] => Mux~1.IN54
ROM_DATA[15] => Mux~2.IN54
ROM_DATA[15] => Mux~3.IN54
ROM_DATA[16] => Mux~0.IN53
ROM_DATA[16] => Mux~1.IN53
ROM_DATA[16] => Mux~2.IN53
ROM_DATA[16] => Mux~3.IN53
ROM_DATA[17] => Mux~0.IN52
ROM_DATA[17] => Mux~1.IN52
ROM_DATA[17] => Mux~2.IN52
ROM_DATA[17] => Mux~3.IN52
ROM_DATA[18] => Mux~0.IN51
ROM_DATA[18] => Mux~1.IN51
ROM_DATA[18] => Mux~2.IN51
ROM_DATA[18] => Mux~3.IN51
ROM_DATA[19] => Mux~0.IN50
ROM_DATA[19] => Mux~1.IN50
ROM_DATA[19] => Mux~2.IN50
ROM_DATA[19] => Mux~3.IN50
ROM_DATA[20] => Mux~0.IN49
ROM_DATA[20] => Mux~1.IN49
ROM_DATA[20] => Mux~2.IN49
ROM_DATA[20] => Mux~3.IN49
ROM_DATA[21] => Mux~0.IN48
ROM_DATA[21] => Mux~1.IN48
ROM_DATA[21] => Mux~2.IN48
ROM_DATA[21] => Mux~3.IN48
ROM_DATA[22] => Mux~0.IN47
ROM_DATA[22] => Mux~1.IN47
ROM_DATA[22] => Mux~2.IN47
ROM_DATA[22] => Mux~3.IN47
ROM_DATA[23] => Mux~0.IN46
ROM_DATA[23] => Mux~1.IN46
ROM_DATA[23] => Mux~2.IN46
ROM_DATA[23] => Mux~3.IN46
ROM_DATA[24] => Mux~0.IN45
ROM_DATA[24] => Mux~1.IN45
ROM_DATA[24] => Mux~2.IN45
ROM_DATA[24] => Mux~3.IN45
ROM_DATA[25] => Mux~0.IN44
ROM_DATA[25] => Mux~1.IN44
ROM_DATA[25] => Mux~2.IN44
ROM_DATA[25] => Mux~3.IN44
ROM_DATA[26] => Mux~0.IN43
ROM_DATA[26] => Mux~1.IN43
ROM_DATA[26] => Mux~2.IN43
ROM_DATA[26] => Mux~3.IN43
ROM_DATA[27] => Mux~0.IN42
ROM_DATA[27] => Mux~1.IN42
ROM_DATA[27] => Mux~2.IN42
ROM_DATA[27] => Mux~3.IN42
ROM_DATA[28] => Mux~0.IN41
ROM_DATA[28] => Mux~1.IN41
ROM_DATA[28] => Mux~2.IN41
ROM_DATA[28] => Mux~3.IN41
ROM_DATA[29] => Mux~0.IN40
ROM_DATA[29] => Mux~1.IN40
ROM_DATA[29] => Mux~2.IN40
ROM_DATA[29] => Mux~3.IN40
ROM_DATA[30] => Mux~0.IN39
ROM_DATA[30] => Mux~1.IN39
ROM_DATA[30] => Mux~2.IN39
ROM_DATA[30] => Mux~3.IN39
ROM_DATA[31] => Mux~0.IN38
ROM_DATA[31] => Mux~1.IN38
ROM_DATA[31] => Mux~2.IN38
ROM_DATA[31] => Mux~3.IN38
ROM_DATA[32] => Mux~0.IN37
ROM_DATA[32] => Mux~1.IN37
ROM_DATA[32] => Mux~2.IN37
ROM_DATA[32] => Mux~3.IN37
ROM_DATA[33] => Mux~0.IN36
ROM_DATA[33] => Mux~1.IN36
ROM_DATA[33] => Mux~2.IN36
ROM_DATA[33] => Mux~3.IN36
ROM_DATA[34] => Mux~0.IN35
ROM_DATA[34] => Mux~1.IN35
ROM_DATA[34] => Mux~2.IN35
ROM_DATA[34] => Mux~3.IN35
ROM_DATA[35] => Mux~0.IN34
ROM_DATA[35] => Mux~1.IN34
ROM_DATA[35] => Mux~2.IN34
ROM_DATA[35] => Mux~3.IN34
ROM_DATA[36] => Mux~0.IN33
ROM_DATA[36] => Mux~1.IN33
ROM_DATA[36] => Mux~2.IN33
ROM_DATA[36] => Mux~3.IN33
ROM_DATA[37] => Mux~0.IN32
ROM_DATA[37] => Mux~1.IN32
ROM_DATA[37] => Mux~2.IN32
ROM_DATA[37] => Mux~3.IN32
ROM_DATA[38] => Mux~0.IN31
ROM_DATA[38] => Mux~1.IN31
ROM_DATA[38] => Mux~2.IN31
ROM_DATA[38] => Mux~3.IN31
ROM_DATA[39] => Mux~0.IN30
ROM_DATA[39] => Mux~1.IN30
ROM_DATA[39] => Mux~2.IN30
ROM_DATA[39] => Mux~3.IN30
ROM_DATA[40] => Mux~0.IN29
ROM_DATA[40] => Mux~1.IN29
ROM_DATA[40] => Mux~2.IN29
ROM_DATA[40] => Mux~3.IN29
ROM_DATA[41] => Mux~0.IN28
ROM_DATA[41] => Mux~1.IN28
ROM_DATA[41] => Mux~2.IN28
ROM_DATA[41] => Mux~3.IN28
ROM_DATA[42] => Mux~0.IN27
ROM_DATA[42] => Mux~1.IN27
ROM_DATA[42] => Mux~2.IN27
ROM_DATA[42] => Mux~3.IN27
ROM_DATA[43] => Mux~0.IN26
ROM_DATA[43] => Mux~1.IN26
ROM_DATA[43] => Mux~2.IN26
ROM_DATA[43] => Mux~3.IN26
ROM_DATA[44] => Mux~0.IN25
ROM_DATA[44] => Mux~1.IN25
ROM_DATA[44] => Mux~2.IN25
ROM_DATA[44] => Mux~3.IN25
ROM_DATA[45] => Mux~0.IN24
ROM_DATA[45] => Mux~1.IN24
ROM_DATA[45] => Mux~2.IN24
ROM_DATA[45] => Mux~3.IN24
ROM_DATA[46] => Mux~0.IN23
ROM_DATA[46] => Mux~1.IN23
ROM_DATA[46] => Mux~2.IN23
ROM_DATA[46] => Mux~3.IN23
ROM_DATA[47] => Mux~0.IN22
ROM_DATA[47] => Mux~1.IN22
ROM_DATA[47] => Mux~2.IN22
ROM_DATA[47] => Mux~3.IN22
TCK => word_counter[2].CLK
TCK => word_counter[1].CLK
TCK => word_counter[0].CLK
TCK => WORD_SR[3].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[0].CLK
TCK => word_counter[3].CLK
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~3.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => WORD_SR[3].ENA
ENA => WORD_SR[2].ENA
ENA => WORD_SR[1].ENA
ENA => WORD_SR[0].ENA
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE