piso.hier_info

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

ROM_DATA[43] => Mux~2.IN26
ROM_DATA[43] => Mux~3.IN26
ROM_DATA[44] => Mux~0.IN25
ROM_DATA[44] => Mux~1.IN25
ROM_DATA[44] => Mux~2.IN25
ROM_DATA[44] => Mux~3.IN25
ROM_DATA[45] => Mux~0.IN24
ROM_DATA[45] => Mux~1.IN24
ROM_DATA[45] => Mux~2.IN24
ROM_DATA[45] => Mux~3.IN24
ROM_DATA[46] => Mux~0.IN23
ROM_DATA[46] => Mux~1.IN23
ROM_DATA[46] => Mux~2.IN23
ROM_DATA[46] => Mux~3.IN23
ROM_DATA[47] => Mux~0.IN22
ROM_DATA[47] => Mux~1.IN22
ROM_DATA[47] => Mux~2.IN22
ROM_DATA[47] => Mux~3.IN22
TCK => word_counter[2].CLK
TCK => word_counter[1].CLK
TCK => word_counter[0].CLK
TCK => WORD_SR[3].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[0].CLK
TCK => word_counter[3].CLK
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~3.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => WORD_SR[3].ENA
ENA => WORD_SR[2].ENA
ENA => WORD_SR[1].ENA
ENA => WORD_SR[0].ENA
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|top|add:s4
poin[0] => LessThan~0.IN18
poin[0] => temp~8.DATAA
poin[1] => LessThan~0.IN17
poin[1] => temp~7.DATAA
poin[2] => LessThan~0.IN16
poin[2] => temp~6.DATAA
poin[3] => LessThan~0.IN15
poin[3] => temp~5.DATAA
poin[4] => LessThan~0.IN14
poin[4] => temp~4.DATAA
poin[5] => LessThan~0.IN13
poin[5] => temp~3.DATAA
poin[6] => LessThan~0.IN12
poin[6] => temp~2.DATAA
poin[7] => LessThan~0.IN11
poin[7] => temp~1.DATAA
poin[8] => LessThan~0.IN10
poin[8] => temp~0.DATAA
poin[9] => ~NO_FANOUT~
poin[10] => ~NO_FANOUT~
poin[11] => ~NO_FANOUT~
poin[12] => ~NO_FANOUT~
poin[13] => ~NO_FANOUT~
poin[14] => ~NO_FANOUT~
poin[15] => ~NO_FANOUT~
poin[16] => ~NO_FANOUT~
poin[17] => ~NO_FANOUT~
poin[18] => ~NO_FANOUT~
poin[19] => ~NO_FANOUT~
poin[20] => ~NO_FANOUT~
poin[21] => ~NO_FANOUT~
poin[22] => ~NO_FANOUT~
poin[23] => ~NO_FANOUT~
poin[24] => ~NO_FANOUT~
poin[25] => ~NO_FANOUT~
poin[26] => ~NO_FANOUT~
poin[27] => ~NO_FANOUT~
poin[28] => reduce_nor~0.IN3
poin[29] => reduce_nor~0.IN2
poin[30] => reduce_nor~0.IN1
poin[31] => reduce_nor~0.IN0
clk => i[30].CLK
clk => i[29].CLK
clk => i[28].CLK
clk => i[27].CLK
clk => i[26].CLK
clk => i[25].CLK
clk => i[24].CLK
clk => i[23].CLK
clk => i[22].CLK
clk => i[21].CLK
clk => i[20].CLK
clk => i[19].CLK
clk => i[18].CLK
clk => i[17].CLK
clk => i[16].CLK
clk => i[15].CLK
clk => i[14].CLK
clk => i[13].CLK
clk => i[12].CLK
clk => i[11].CLK
clk => i[10].CLK
clk => i[9].CLK
clk => i[8].CLK
clk => i[7].CLK
clk => i[6].CLK
clk => i[5].CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => stand[8]~reg0.CLK
clk => stand[7]~reg0.CLK
clk => stand[6]~reg0.CLK
clk => stand[5]~reg0.CLK
clk => stand[4]~reg0.CLK
clk => stand[3]~reg0.CLK
clk => stand[2]~reg0.CLK
clk => stand[1]~reg0.CLK
clk => stand[0]~reg0.CLK
clk => sinout[8]~reg0.CLK
clk => sinout[7]~reg0.CLK
clk => sinout[6]~reg0.CLK
clk => sinout[5]~reg0.CLK
clk => sinout[4]~reg0.CLK
clk => sinout[3]~reg0.CLK
clk => sinout[2]~reg0.CLK
clk => sinout[1]~reg0.CLK
clk => sinout[0]~reg0.CLK
clk => i[31].CLK
en => temp[7].CLK
en => temp[6].CLK
en => temp[5].CLK
en => temp[4].CLK
en => temp[3].CLK
en => temp[2].CLK
en => temp[1].CLK
en => temp[0].CLK
en => change.CLK
en => temp[8].CLK
sinout[0] <= sinout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[1] <= sinout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[2] <= sinout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[3] <= sinout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[4] <= sinout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[5] <= sinout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[6] <= sinout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[7] <= sinout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[8] <= sinout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[0] <= stand[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[1] <= stand[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[2] <= stand[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[3] <= stand[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[4] <= stand[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[5] <= stand[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[6] <= stand[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[7] <= stand[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stand[8] <= stand[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|sin_rom:s5
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|top|sin_rom:s5|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_qjs:auto_generated.address_a[0]
address_a[1] => altsyncram_qjs:auto_generated.address_a[1]
address_a[2] => altsyncram_qjs:auto_generated.address_a[2]
address_a[3] => altsyncram_qjs:auto_generated.address_a[3]
address_a[4] => altsyncram_qjs:auto_generated.address_a[4]
address_a[5] => altsyncram_qjs:auto_generated.address_a[5]
address_a[6] => altsyncram_qjs:auto_generated.address_a[6]
address_a[7] => altsyncram_qjs:auto_generated.address_a[7]
address_a[8] => altsyncram_qjs:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qjs:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_qjs:auto_generated.q_a[0]
q_a[1] <= altsyncram_qjs:auto_generated.q_a[1]
q_a[2] <= altsyncram_qjs:auto_generated.q_a[2]
q_a[3] <= altsyncram_qjs:auto_generated.q_a[3]
q_a[4] <= altsyncram_qjs:auto_generated.q_a[4]
q_a[5] <= altsyncram_qjs:auto_generated.q_a[5]
q_a[6] <= altsyncram_qjs:auto_generated.q_a[6]
q_a[7] <= altsyncram_qjs:auto_generated.q_a[7]
q_b[0] <= <UNC>


|top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated
address_a[0] => altsyncram_gaa2:altsyncram1.address_a[0]
address_a[1] => altsyncram_gaa2:altsyncram1.address_a[1]
address_a[2] => altsyncram_gaa2:altsyncram1.address_a[2]
address_a[3] => altsyncram_gaa2:altsyncram1.address_a[3]
address_a[4] => altsyncram_gaa2:altsyncram1.address_a[4]
address_a[5] => altsyncram_gaa2:altsyncram1.address_a[5]
address_a[6] => altsyncram_gaa2:altsyncram1.address_a[6]
address_a[7] => altsyncram_gaa2:altsyncram1.address_a[7]
address_a[8] => altsyncram_gaa2:altsyncram1.address_a[8]
clock0 => altsyncram_gaa2:altsyncram1.clock0
q_a[0] <= altsyncram_gaa2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_gaa2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_gaa2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_gaa2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_gaa2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_gaa2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_gaa2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_gaa2:altsyncram1.q_a[7]


|top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
address_b[8] => ram_block3a0.PORTBADDR8
address_b[8] => ram_block3a1.PORTBADDR8
address_b[8] => ram_block3a2.PORTBADDR8