piso.hier_info

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

|top
f <= pf:s1.f
si => piso:s2.sI
sck => piso:s2.clock
clk => sin_rom:s5.clock
clk => sin_rom:s3.clock
clk => pf:s1.clk
load => piso:s2.load
st[0] <= <GND>
st[1] <= <GND>
st[2] <= <GND>
st[3] <= <GND>
st[4] <= <GND>
st[5] <= <GND>
st[6] <= <GND>
st[7] <= <GND>
st[8] <= <GND>
fout[0] <= sin_rom:s3.q[0]
fout[1] <= sin_rom:s3.q[1]
fout[2] <= sin_rom:s3.q[2]
fout[3] <= sin_rom:s3.q[3]
fout[4] <= sin_rom:s3.q[4]
fout[5] <= sin_rom:s3.q[5]
fout[6] <= sin_rom:s3.q[6]
fout[7] <= sin_rom:s3.q[7]
pout[0] <= sin_rom:s5.q[0]
pout[1] <= sin_rom:s5.q[1]
pout[2] <= sin_rom:s5.q[2]
pout[3] <= sin_rom:s5.q[3]
pout[4] <= sin_rom:s5.q[4]
pout[5] <= sin_rom:s5.q[5]
pout[6] <= sin_rom:s5.q[6]
pout[7] <= sin_rom:s5.q[7]


|top|pf:s1
clk => \P1:cnt[14].CLK
clk => \P1:cnt[13].CLK
clk => \P1:cnt[12].CLK
clk => \P1:cnt[11].CLK
clk => \P1:cnt[10].CLK
clk => \P1:cnt[9].CLK
clk => \P1:cnt[8].CLK
clk => \P1:cnt[7].CLK
clk => \P1:cnt[6].CLK
clk => \P1:cnt[5].CLK
clk => \P1:cnt[4].CLK
clk => \P1:cnt[3].CLK
clk => \P1:cnt[2].CLK
clk => \P1:cnt[1].CLK
clk => \P1:cnt[0].CLK
clk => flag.CLK
clk => yout~reg0.CLK
clk => f~reg0.CLK
clk => \P1:cnt[15].CLK
en => b[14].CLK
en => b[13].CLK
en => b[12].CLK
en => b[11].CLK
en => b[10].CLK
en => b[9].CLK
en => b[8].CLK
en => b[7].CLK
en => b[6].CLK
en => b[5].CLK
en => b[4].CLK
en => b[3].CLK
en => b[2].CLK
en => b[1].CLK
en => b[0].CLK
en => b[15].CLK
yout <= yout~reg0.DB_MAX_OUTPUT_PORT_TYPE
f <= f~reg0.DB_MAX_OUTPUT_PORT_TYPE
d[0] => b[0].DATAIN
d[1] => b[1].DATAIN
d[2] => b[2].DATAIN
d[3] => b[3].DATAIN
d[4] => b[4].DATAIN
d[5] => b[5].DATAIN
d[6] => b[6].DATAIN
d[7] => b[7].DATAIN
d[8] => b[8].DATAIN
d[9] => b[9].DATAIN
d[10] => b[10].DATAIN
d[11] => b[11].DATAIN
d[12] => b[12].DATAIN
d[13] => b[13].DATAIN
d[14] => b[14].DATAIN
d[15] => b[15].DATAIN
change[0] => reduce_nor~0.IN0
change[1] => reduce_nor~0.IN1
change[2] => reduce_nor~0.IN2
change[3] => reduce_nor~0.IN3


|top|piso:s2
load => i[3].ACLR
load => i[2].ACLR
load => i[1].ACLR
load => i[0].ACLR
load => i[4].ACLR
load => en.DATAIN
clock => po[30]~reg0.CLK
clock => po[29]~reg0.CLK
clock => po[28]~reg0.CLK
clock => po[27]~reg0.CLK
clock => po[26]~reg0.CLK
clock => po[25]~reg0.CLK
clock => po[24]~reg0.CLK
clock => po[23]~reg0.CLK
clock => po[22]~reg0.CLK
clock => po[21]~reg0.CLK
clock => po[20]~reg0.CLK
clock => po[19]~reg0.CLK
clock => po[18]~reg0.CLK
clock => po[17]~reg0.CLK
clock => po[16]~reg0.CLK
clock => po[15]~reg0.CLK
clock => po[14]~reg0.CLK
clock => po[13]~reg0.CLK
clock => po[12]~reg0.CLK
clock => po[11]~reg0.CLK
clock => po[10]~reg0.CLK
clock => po[9]~reg0.CLK
clock => po[8]~reg0.CLK
clock => po[7]~reg0.CLK
clock => po[6]~reg0.CLK
clock => po[5]~reg0.CLK
clock => po[4]~reg0.CLK
clock => po[3]~reg0.CLK
clock => po[2]~reg0.CLK
clock => po[1]~reg0.CLK
clock => po[0]~reg0.CLK
clock => i[4].CLK
clock => i[3].CLK
clock => i[2].CLK
clock => i[1].CLK
clock => i[0].CLK
clock => po[31]~reg0.CLK
po[0] <= po[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[1] <= po[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[2] <= po[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[3] <= po[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[4] <= po[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[5] <= po[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[6] <= po[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[7] <= po[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[8] <= po[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[9] <= po[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[10] <= po[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[11] <= po[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[12] <= po[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[13] <= po[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[14] <= po[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[15] <= po[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[16] <= po[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[17] <= po[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[18] <= po[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[19] <= po[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[20] <= po[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[21] <= po[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[22] <= po[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[23] <= po[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[24] <= po[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[25] <= po[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[26] <= po[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[27] <= po[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[28] <= po[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[29] <= po[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[30] <= po[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
po[31] <= po[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sI => po[30]~reg0.DATAIN
sI => po[29]~reg0.DATAIN
sI => po[28]~reg0.DATAIN
sI => po[27]~reg0.DATAIN
sI => po[26]~reg0.DATAIN
sI => po[25]~reg0.DATAIN
sI => po[24]~reg0.DATAIN
sI => po[23]~reg0.DATAIN
sI => po[22]~reg0.DATAIN
sI => po[21]~reg0.DATAIN
sI => po[20]~reg0.DATAIN
sI => po[19]~reg0.DATAIN
sI => po[18]~reg0.DATAIN
sI => po[17]~reg0.DATAIN
sI => po[16]~reg0.DATAIN
sI => po[15]~reg0.DATAIN
sI => po[14]~reg0.DATAIN
sI => po[13]~reg0.DATAIN
sI => po[12]~reg0.DATAIN
sI => po[11]~reg0.DATAIN
sI => po[10]~reg0.DATAIN
sI => po[9]~reg0.DATAIN
sI => po[8]~reg0.DATAIN
sI => po[7]~reg0.DATAIN
sI => po[6]~reg0.DATAIN
sI => po[5]~reg0.DATAIN
sI => po[4]~reg0.DATAIN
sI => po[3]~reg0.DATAIN
sI => po[2]~reg0.DATAIN
sI => po[1]~reg0.DATAIN
sI => po[0]~reg0.DATAIN
sI => po[31]~reg0.DATAIN
en <= load.DB_MAX_OUTPUT_PORT_TYPE


|top|sin_rom:s3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|top|sin_rom:s3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_qjs:auto_generated.address_a[0]
address_a[1] => altsyncram_qjs:auto_generated.address_a[1]
address_a[2] => altsyncram_qjs:auto_generated.address_a[2]
address_a[3] => altsyncram_qjs:auto_generated.address_a[3]
address_a[4] => altsyncram_qjs:auto_generated.address_a[4]
address_a[5] => altsyncram_qjs:auto_generated.address_a[5]
address_a[6] => altsyncram_qjs:auto_generated.address_a[6]
address_a[7] => altsyncram_qjs:auto_generated.address_a[7]
address_a[8] => altsyncram_qjs:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qjs:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_qjs:auto_generated.q_a[0]
q_a[1] <= altsyncram_qjs:auto_generated.q_a[1]
q_a[2] <= altsyncram_qjs:auto_generated.q_a[2]
q_a[3] <= altsyncram_qjs:auto_generated.q_a[3]
q_a[4] <= altsyncram_qjs:auto_generated.q_a[4]
q_a[5] <= altsyncram_qjs:auto_generated.q_a[5]
q_a[6] <= altsyncram_qjs:auto_generated.q_a[6]
q_a[7] <= altsyncram_qjs:auto_generated.q_a[7]
q_b[0] <= <UNC>


|top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated
address_a[0] => altsyncram_gaa2:altsyncram1.address_a[0]
address_a[1] => altsyncram_gaa2:altsyncram1.address_a[1]
address_a[2] => altsyncram_gaa2:altsyncram1.address_a[2]
address_a[3] => altsyncram_gaa2:altsyncram1.address_a[3]
address_a[4] => altsyncram_gaa2:altsyncram1.address_a[4]
address_a[5] => altsyncram_gaa2:altsyncram1.address_a[5]
address_a[6] => altsyncram_gaa2:altsyncram1.address_a[6]
address_a[7] => altsyncram_gaa2:altsyncram1.address_a[7]
address_a[8] => altsyncram_gaa2:altsyncram1.address_a[8]
clock0 => altsyncram_gaa2:altsyncram1.clock0
q_a[0] <= altsyncram_gaa2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_gaa2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_gaa2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_gaa2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_gaa2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_gaa2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_gaa2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_gaa2:altsyncram1.q_a[7]


|top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2