top.vhd

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

library ieee;
use ieee.std_logic_1164.all;

entity top is 
	port(
		f: out std_logic;
		si : in std_logic;
		sck, clk : in std_logic;
		load : in std_logic;
		 st  :out std_logic_vector(8 downto 0);
		 fout, pout: out std_logic_vector(7 downto 0));
end top;

architecture top_1 of top is

component pf
	port (clk  : in std_logic;
		 en	: in std_logic;
         yout, f : out std_logic;
          d   : in  std_logic_vector(15 downto 0);
		 change : in std_logic_vector(3 downto 0));
end component;
--------------------------------------------------------
component piso
port (load : in std_logic;
        clock:in std_logic;
        po:out std_logic_vector(31 downto 0);
		--a, b ,c: out std_logic;
        sI:IN std_logic;
		en: out std_logic);
end component;
-----------------------------------------------------
component  add
port(poin : in std_logic_vector(31 downto 0);
        clk : in std_logic;
          en: in std_logic;
sinout,stand:out std_logic_vector(8 downto 0));
end component;
------------------------------------------------------------
component sin_rom
PORT (
		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;
-----------------------------------------------------------------
signal temp : std_logic_vector(31 downto 0);
signal temp2 ,temp3,temp5: std_logic;
signal temp4, temp6: std_logic_vector(8 downto 0);
begin
	s1 : pf port map(clk, temp2, temp3, f, temp(15 downto 0), temp(31 downto 28));
	s2 : piso port map(load, sck, temp, si, temp2);
	s3 : sin_rom port map( temp4,clk, fout(7 downto 0));
	s4 : add port map(temp,temp3,temp2,temp4,temp6);
	s5 : sin_rom port map( temp6, clk, pout);
	
end top_1;