pf.vhd

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pf is
  port ( clk  : in std_logic;
		 en	: in std_logic;
         yout, f : out std_logic;
          d   : in  std_logic_vector(15 downto 0);
		 change : in std_logic_vector(3 downto 0));
end pf;

architecture pf_1024 of pf is
	signal flag :std_logic;
	signal b: std_logic_vector(15 downto 0);
begin
---------------------------------------
P3: process(en, change)
begin
	if (en'event and en ='1') then
		if change = "1111" then
 			b <= d;
		end if;
	end if;
end process P3;
-----------------------------------------
P1: process(clk)
variable cnt:std_logic_vector(15 downto 0);
begin
if clk'event and clk = '1' then
  if cnt=x"ffff" then 
    cnt:=b;
 --   flag<='1';
 -- else cnt:=cnt+1;
 --   flag<='0';
	flag <= not flag;
	yout <= flag;
	f <= flag;
  end if;
end if;
end process P1;
--------------------------------------------
--P2: process(yout)
--variable cnt2 :std_logic;
--begin
--if flag'event and flag='1' then
--  cnt2:=not cnt2;
--    if cnt2='1' then 
--		yout<='1';
--		f <= '1';
--     else 
--		yout<='0';
--		f <= '0';
--    end if;
--end if;
--end process P2;
end pf_1024;