mux_r.v

来自「一个支持精简指令的16位的risc cpu」· Verilog 代码 · 共 18 行

//11	from_pc
//01 alu[15:14]=0	alu_out
//00	from_mem
//10	i1
module mux_r(alu_out,from_pc,from_mem,i1,mux_out,mux_r);
output	[15:0]	mux_out;
input	[15:0]	alu_out;
input	[15:0]	from_pc;
input	[15:0]	from_mem;
input	[7:0]	i1;
input	[1:0]	mux_r;

assign mux_out = ((~mux_r[1]) && (~mux_r[0])) ? from_mem :((~mux_r[1]) && (mux_r[0]))? alu_out:((mux_r[1]) && (~mux_r[0]))? {{8'b00000000},i1}: from_pc;

endmodule