ram.v

来自「一个支持精简指令的16位的risc cpu」· Verilog 代码 · 共 20 行

`timescale 10ns/1ns
module ram(data_in,data_out,addr,read,write);
output	[15:0]	data_out;
input	[15:0]	data_in;
input	[15:0]	addr;
input	read,write;

reg	[15:0] memory[16'hffff:0];

assign data_out=(read)? memory[addr]:16'hzzzz;

  always @ (posedge write)
    begin
      memory[addr]<=data_in;
    end


endmodule