machine.v

一个支持精简指令的16位的risc cpu

                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b001;   
                      end
              else
                   if(opcode==RSHU)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0010;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b010;   
                      end
              else
                   if(opcode==JR)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0100;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000100;
                      mux_r <=2'b11;
                      alu_c <=3'b000;   
                      end
		else
			if(opcode==J)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b1000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000100;
                      mux_r <=2'b11;
                      alu_c <=3'b000;   
                      end

              else
                   if(opcode==BZ)
                      begin
                      if(d1_in==16'b0000_0000_0000_0000)
                          begin
                          {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
                          {mux_p1,mux_p2,mux_a,mux_pa} <=4'b1100;
                          {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                          mux_r <=2'b00;
                          alu_c <=3'b000;
                          end
                      else
                          begin
                           {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
                           {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                           {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                           mux_r <=2'b00;
                           alu_c <=3'b000;
                         end   
                      end
              else
                   if(opcode==BNZ)
               	begin
                      if(d1_in!=16'b0000_0000_0000_0000)
                          begin
                          {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
                          {mux_p1,mux_p2,mux_a,mux_pa} <=4'b1100;
                          {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                          mux_r <=2'b00;
                          alu_c <=3'b000;
                          end
                      else
                          begin
                           {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
                           {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                           {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                           mux_r <=2'b00;
                           alu_c <=3'b000;
                         end   
                      end
              else
                   begin
                          {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                          {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                          {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                          mux_r <=2'b00;
                          alu_c <=3'b000;
                   end
              state <=3'b011;
        end


3'b011:
        begin
              if(opcode==L||opcode==S)
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00001;////load_pa
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0001;
                 {r,w,h,w_r,r_r,d1_ena} <=6'b000000;//change
                 mux_r <=2'b00;
                 alu_c <=3'b000;
                 end
              else
                   if(opcode==ADD||opcode==SUB||opcode==AND||opcode==OR||opcode==NOT||opcode==LSH||opcode==RSH||opcode==RSHU)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000100;                           
                      mux_r <=2'b01;//ch
                      alu_c <=3'b000;
                      end
              else
                   begin
                          {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                          {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                          {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                          mux_r <=2'b00;
                          alu_c <=3'b000;
                   end
              state <=3'b100;
        end


3'b100:
        begin
              if(opcode==L)
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                 {r,w,h,w_r,r_r,d1_ena} <=6'b100100;//change
                 mux_r <=2'b00;
                 alu_c <=3'b000;
                 end
              else 
                   if(opcode==S)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000011;//change                           
                      mux_r <=2'b00;
                      alu_c <=3'b000;
                      end
              else
                   begin
                          {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                          {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                          {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                          mux_r <=2'b00;
                          alu_c <=3'b000;
                   end
              state <=3'b101;
        end


3'b101:
	begin
		 if(opcode==S)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b010000;                           
                      mux_r <=2'b00;
                      alu_c <=3'b000;
                      end
		state <= 3'b110;
	end



3'b110:
        begin
              if(opcode==L||opcode==S||opcode==LI||opcode==ADD||opcode==SUB||opcode==AND||opcode==OR||opcode==NOT||opcode==LSH||opcode==RSH||opcode==RSHU)
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;//change
                 {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                 mux_r <=2'b00;
                 alu_c <=3'b000;
                 end
              else
                   begin
                          {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                          {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                          {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
                          mux_r <=2'b00;
                          alu_c <=3'b000;
                   end
              state <=3'b111;
        end


3'b111:
        begin
              {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00001;
              {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
              {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
              mux_r <=2'b00;
              alu_c <=3'b000;
		state <= 3'b000;
        end



default:
        begin
              {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
              {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
              {r,w,h,w_r,r_r,d1_ena} <=6'b000000;                           
              mux_r <=2'b00;
              alu_c <=3'b000;
		state <= 3'b000;
        end

endcase

end

endtask

//------------------------end of task clk_cycle-------------------



endmodule