📄 risc_cpu.v
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always @(A_IN or B_EFF or OP_IN[2])
RESULT = A_IN + B_EFF + OP_IN[2];
endmodule // arithmetic
// logic: execution of logic operations
//
// Operations:
// 3'b101: RESULT = A AND B
// 3'b110: RESULT = A OR B
// 3'b100: RESULT = not B
//
//----------------------------------------------------------------------------
module logic (RESULT,A_IN, B_IN, OP_IN);
output [15:0] RESULT; // output result
input [15:0] A_IN, // input operand A
B_IN; // input operand B
input [ 2:0] OP_IN; // input opcode
reg [15:0] RESULT; // result
wire [15:0] A_IN, // operand A
B_IN; // operand B
wire [2:0] OP_IN; // opcode
//wire [15:0] result;
//assign result = RESULT;
//assign result = ~A_IN ;
always @(A_IN or B_IN or OP_IN)
begin
case(OP_IN)
3'b101: RESULT = A_IN & B_IN; // AND
3'b110: RESULT = A_IN | B_IN; // OR
endcase
end
endmodule // logic
//----------------------------------------------------------------------------
//
// shift: execute shift operations
//
// Operations:
// 3'b000: RESULT = A << B left shift
// 3'b010: RESULT = A >> B right shift
// 3'b001: RESULT = A ASR B right shift (sign maintaining)
module shift (RESULT,A_IN, B_IN, OP_IN);
output [15:0] RESULT; // output result
input [15:0] A_IN; // input operand A
input [ 4:0] B_IN; // input operand B
input [ 2:0] OP_IN; // input opcode
reg [15:0] RESULT; // result
reg [15:0] SIGN_mask;
wire [15:0] A_IN; // operand A
wire [ 4:0] B_IN; // operand B
wire [ 2:0] OP_IN; // opcode
always @ (A_IN or B_IN or OP_IN)
begin
if(OP_IN == 3'b000)
RESULT <= A_IN << B_IN;
else if(OP_IN == 3'b010)
RESULT <= A_IN >> B_IN;
else if(OP_IN == 3'b001)
begin
SIGN_mask <= ~({16{A_IN[15]}} >> B_IN);
RESULT <= SIGN_mask | A_IN;
end
end
endmodule
//***************************clk1.v*****************************
module clk1(clk,clk1);
input clk;
output clk1;
assign clk1 = ~clk;
endmodule
//***************************counter.v******************************
//`timescale 10ns/1ns
module counter(pc_addr,to_d1,base_addr,bias_addr,op_j,op_jr,load_pc,reset);
output [15:0] pc_addr,to_d1;
input [15:0] base_addr;
input [7:0] bias_addr;
input load_pc,reset,op_j,op_jr;
reg [15:0] pc_addr,to_d1;
always @ (posedge reset or posedge load_pc)
begin
if(reset)
begin
pc_addr <= 16'b0000_0000_0000_0000;
to_d1 <= 16'b0000_0000_0000_0000;
end
else if(load_pc)
begin
if(op_j&&(~op_jr))
begin
pc_addr <= pc_addr + {{8{bias_addr[7]}},bias_addr};
to_d1 <= pc_addr + 1;
end
else if(op_jr&&(~op_j))
begin
pc_addr <= base_addr + {{8{bias_addr[7]}},bias_addr};
to_d1 <= pc_addr + 1;
end
else if(op_j&&op_jr)
begin
pc_addr <= pc_addr + {{8{bias_addr[7]}},bias_addr};
to_d1 <= 16'bzzzz_zzzz_zzzz_zzzz;
end
else
begin
pc_addr <= pc_addr + 1;
to_d1 <= 16'bzzzz_zzzz_zzzz_zzzz;
end
end
end
endmodule
//****************************group_reg.v*******************************
module group_reg(clk1,d1_ena,load_gpr,r_r,w_r,reset,d1,d2,d3,data_in,data_out1or2,data_out3);
output [15:0] data_out1or2,data_out3;
input [15:0] data_in;
input [2:0] d1,d2,d3;
input reset,clk1,d1_ena,load_gpr,r_r,w_r;
wire [15:0] data_out1or2,data_out3;
wire r_d1,r_d2,r_d3,w;
assign r_d1=load_gpr && r_r && d1_ena;
assign r_d2=load_gpr && r_r && (~d1_ena);
assign r_d3=load_gpr && r_r && (~d1_ena);
assign w=load_gpr && w_r;
reg1 m_reg1(.clk1(clk1),.reset(reset),.d1(d1),.d2(d2),.r_d1(r_d1),.r_d2(r_d2),.w(w),.data_in(data_in),
.m0(data_out1or2),.m1(data_out1or2),.m2(data_out1or2),.m3(data_out1or2),
.m4(data_out1or2),.m5(data_out1or2),.m6(data_out1or2),.m7(data_out1or2));
reg2 m_reg2(.clk1(clk1),.reset(reset),.d1(d1),.d3(d3),.r_d3(r_d3),.w(w),.data_in(data_in),
.m0(data_out3),.m1(data_out3),.m2(data_out3),.m3(data_out3),
.m4(data_out3),.m5(data_out3),.m6(data_out3),.m7(data_out3));
endmodule
module reg1(clk1,reset,d1,d2,r_d1,r_d2,w,data_in,m0,m1,m2,m3,m4,m5,m6,m7);
output [15:0] m0,m1,m2,m3,m4,m5,m6,m7;
input [15:0] data_in;
input [2:0] d1,d2;
input clk1,reset,r_d1,r_d2,w;
reg [15:0] r0,r1,r2,r3,r4,r5,r6,r7;
reg [15:0] m0,m1,m2,m3,m4,m5,m6,m7;
always @ (posedge clk1)
begin
if(reset)
begin
r0<=0;r1<=0;r2<=0;r3<=0;r4<=0;r5<=0;r6<=0;r7<=0;
m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz;
end
else if(w)
begin
case(d1)
3'b000:r0<=r0;
3'b001:r1<=data_in;
3'b010:r2<=data_in;
3'b011:r3<=data_in;
3'b100:r4<=data_in;
3'b101:r5<=data_in;
3'b110:r6<=data_in;
3'b111:r7<=data_in;
endcase
end
else if(r_d1)
begin
case(d1)
3'b000:begin m0<=0;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b001:begin m0<=16'hzzzz;m1<=r1;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b010:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=r2;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b011:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=r3;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b100:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=r4;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b101:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=r5;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b110:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=r6;m7<=16'hzzzz; end
3'b111:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=r7; end
endcase
end
else if(r_d2)
begin
case(d2)
3'b000:begin m0<=0;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b001:begin m0<=16'hzzzz;m1<=r1;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b010:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=r2;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b011:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=r3;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b100:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=r4;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b101:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=r5;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b110:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=r6;m7<=16'hzzzz; end
3'b111:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=r7; end
endcase
end
end
endmodule
module reg2(clk1,reset,d1,d3,r_d3,w,data_in,m0,m1,m2,m3,m4,m5,m6,m7);
output [15:0] m0,m1,m2,m3,m4,m5,m6,m7;
input [15:0] data_in;
input [2:0] d1,d3;
input clk1,reset,r_d3,w;
reg [15:0] r0,r1,r2,r3,r4,r5,r6,r7;
reg [15:0] m0,m1,m2,m3,m4,m5,m6,m7;
always @ (posedge clk1)
begin
if(reset)
begin
r0<=0;r1<=0;r2<=0;r3<=0;r4<=0;r5<=0;r6<=0;r7<=0;
m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz;
end
else if(w)
begin
case(d1)
3'b000:r0<=r0;
3'b001:r1<=data_in;
3'b010:r2<=data_in;
3'b011:r3<=data_in;
3'b100:r4<=data_in;
3'b101:r5<=data_in;
3'b110:r6<=data_in;
3'b111:r7<=data_in;
endcase
end
else if(r_d3)
begin
case(d3)
3'b000:begin m0<=0;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b001:begin m0<=16'hzzzz;m1<=r1;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b010:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=r2;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b011:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=r3;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b100:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=r4;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b101:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=r5;m6<=16'hzzzz;m7<=16'hzzzz; end
3'b110:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=r6;m7<=16'hzzzz; end
3'b111:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=r7; end
endcase
end
end
endmodule
//*****************************mux_r.v*****************************
//11 from_pc
//01 alu[15:14]=0 alu_out
//00 from_mem
//10 i1
module mux_r(alu_out,from_pc,from_mem,i1,mux_out,mux_r);
output [15:0] mux_out;
input [15:0] alu_out;
input [15:0] from_pc;
input [15:0] from_mem;
input [7:0] i1;
input [1:0] mux_r;
assign mux_out = ((~mux_r[1]) && (~mux_r[0])) ? from_mem :((~mux_r[1]) && (mux_r[0]))? alu_out:((mux_r[1]) && (~mux_r[0]))? {{8'b00000000},i1}: from_pc;
endmodule
//******************************mux_a.v*****************************
//`timescale 10ns/1ns
module mux_a(data_in3,i2,b_bus,lors);
output [15:0] b_bus;
input [15:0] data_in3;
input [4:0] i2;
input lors;
assign b_bus = (lors)? {{11{i2[4]}},i2} : data_in3;
endmodule
//******************************register.v****************************
//`timescale 10ns/1ns
module register(data,ena,clk1,opc_iraddrs);
input [15:0] data;
input ena,clk1;
output [15:0] opc_iraddrs;
reg [15:0] opc_iraddrs;
always @ (posedge clk1)
begin
if(ena)
opc_iraddrs[15:0] <= data[15:0];
end
endmodule
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