📄 risc_cpu.v
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{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01100;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b1000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000100;
mux_r <=2'b11;
alu_c <=3'b000;
end
else
if(opcode==BZ)
begin
if(d1_in==16'b0000_0000_0000_0000)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b1100;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
else
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
end
else
if(opcode==BNZ)
begin
if(d1_in!=16'b0000_0000_0000_0000)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b1100;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
else
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
end
else
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
state <=3'b011;
end
3'b011:
begin
if(opcode==L||opcode==S)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00001;////load_pa
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0001;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;//change
mux_r <=2'b00;
alu_c <=3'b000;
end
else
if(opcode==ADD||opcode==SUB||opcode==AND||opcode==OR||opcode==NOT||opcode==LSH||opcode==RSH||opcode==RSHU)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000100;
mux_r <=2'b01;//ch
alu_c <=3'b000;
end
else
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
state <=3'b100;
end
3'b100:
begin
if(opcode==L)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b100100;//change
mux_r <=2'b00;
alu_c <=3'b000;
end
else
if(opcode==S)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000011;//change
mux_r <=2'b00;
alu_c <=3'b000;
end
else
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
state <=3'b101;
end
3'b101:
begin
if(opcode==S)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b010000;
mux_r <=2'b00;
alu_c <=3'b000;
end
state <= 3'b110;
end
3'b110:
begin
if(opcode==L||opcode==S||opcode==LI||opcode==ADD||opcode==SUB||opcode==AND||opcode==OR||opcode==NOT||opcode==LSH||opcode==RSH||opcode==RSHU)
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;//change
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
else
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
end
state <=3'b111;
end
3'b111:
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00001;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
state <= 3'b000;
end
default:
begin
{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
{r,w,h,w_r,r_r,d1_ena} <=6'b000000;
mux_r <=2'b00;
alu_c <=3'b000;
state <= 3'b000;
end
endcase
end
endtask
//------------------------end of task clk_cycle-------------------
endmodule
//***************************addreg.v********************
module addreg(clk1,addr,reset,load_pa,mux_pa,pc_addr,alu_out);
output [15:0] addr;
input [15:0] pc_addr,alu_out;
input reset,load_pa,mux_pa,clk1;
reg [15:0] addr;
always @ (clk1)
begin
if(reset)
addr <= 16'h0000;
else if(load_pa)
begin
if(mux_pa)
addr <= alu_out;
else if(~mux_pa)
addr <= pc_addr;
end
end
endmodule
//****************************alu.v******************************
//Operations:
// 3'b100: C3 = A not B\
// 3'b101: C3 = A OR B | logic instructions
// 3'b110: C3 = A AND B/
// 3'b000: C3 = A << B \
// 3'b010: C3 = A >> B | shift
// 3'b001: C3 = A ASR B | instructions
// 3'b011: C3 = A + B \ arithmetic
// 3'b111: C3 = A - B | instructions
module alu (C3_BUS, A_BUS, B_BUS, ALU_OPCODE,CP, WORK_EX);
output [15:0] C3_BUS; // result bus
//output zero;
input [15:0] A_BUS, // operand bus A
B_BUS; // operand bus B
input [ 2:0] ALU_OPCODE; // opcode
input CP, // processor clock
WORK_EX; // work enable
reg [15:0] C3_BUS; // result
//reg zero;
wire [15:0] A_BUS, // operand bus A
B_BUS; // operand bus B
wire [ 2:0] ALU_OPCODE; // opcode
wire CP, // processor clock
WORK_EX; // work enable
reg [15:0] ALU_AREG, // operand register A
ALU_BREG; // operand register B
reg [ 2:0] ALU_OREG; // opcode register
wire [15:0] ARITH_RES, // result of ARITHMETIC
LOGIC_RES, // result of LOGIC
SHIFT_RES; // result of SHIFT
arithmetic ARITHMETIC (ARITH_RES, ALU_AREG, ALU_BREG, ALU_OREG);
logic LOGIC (LOGIC_RES, ALU_AREG, ALU_BREG, ALU_OREG);
shift SHIFT (SHIFT_RES, ALU_AREG, ALU_BREG[4:0], ALU_OREG);
// Read inputs with rising clock edge,
// if work enable
always @(posedge CP)
begin
if (WORK_EX)
begin
ALU_AREG = A_BUS;
ALU_BREG = B_BUS;
ALU_OREG = ALU_OPCODE;
//zero = (| LOGIC_RES ) || (| SHIFT_RES ) || (| ARITH_RES );
end
end
always @(ARITH_RES or LOGIC_RES or SHIFT_RES or ALU_OREG)
begin
casex(ALU_OREG[2:0])
3'b10x: C3_BUS = LOGIC_RES; // logic operations
3'b110: C3_BUS = LOGIC_RES; // logic operations
3'b00x: C3_BUS = SHIFT_RES; // shift operations
3'b010: C3_BUS = SHIFT_RES; // shift operations
3'bx11: C3_BUS = ARITH_RES; // arithmetic operations
endcase
end
endmodule
// arithmetic: execution of arithmetic operations
//
// Operations:
// 3'b011: RESULT = A_IN + B_IN
// 3'b111: RESULT = A_IN - B_IN
module arithmetic ( RESULT,A_IN, B_IN, OP_IN);
output [15:0] RESULT; // output result
input [15:0] A_IN, // input operand A
B_IN; // input operand B
input [2:0] OP_IN; // input opcode
reg [15:0] RESULT; // result
wire [15:0] A_IN, // operand A
B_IN; // operand B
wire [2:0] OP_IN; // opcode
reg [15:0] B_EFF; // operand B to be added effectively
always @(B_IN or OP_IN)
B_EFF = B_IN ^ {16{OP_IN[2]}};
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