📄 mux_2.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L4 is clko~8 at LC_X1_Y1_N2
--operation mode is normal
A1L4 = sel & (clk1) # !sel & clk2;
--clk1 is clk1 at PIN_AD3
--operation mode is input
clk1 = INPUT();
--clk2 is clk2 at PIN_AC4
--operation mode is input
clk2 = INPUT();
--sel is sel at PIN_AD5
--operation mode is input
sel = INPUT();
--clko is clko at PIN_AC5
--operation mode is output
clko = OUTPUT(A1L4);
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