mux_2.map.qmsg

二进制数据或者频率信号选择器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 22:46:07 2005 " "Info: Processing started: Wed Dec 14 22:46:07 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mux_2 -c mux_2 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mux_2 -c mux_2 --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux_2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mux_2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_2-mux_2_arch " "Info: Found design unit 1: mux_2-mux_2_arch" {  } { { "mux_2.vhd" "" { Text "C:/altera/project/experiment/mux2/mux_2.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 mux_2 " "Info: Found entity 1: mux_2" {  } { { "mux_2.vhd" "" { Text "C:/altera/project/experiment/mux2/mux_2.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mux_2 " "Info: Elaborating entity \"mux_2\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1 mux_2.vhd(21) " "Warning: VHDL Process Statement warning at mux_2.vhd(21): signal \"clk1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_2.vhd" "" { Text "C:/altera/project/experiment/mux2/mux_2.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk2 mux_2.vhd(23) " "Warning: VHDL Process Statement warning at mux_2.vhd(23): signal \"clk2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_2.vhd" "" { Text "C:/altera/project/experiment/mux2/mux_2.vhd" 23 0 0 } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 22:46:09 2005 " "Info: Processing ended: Wed Dec 14 22:46:09 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}