mux_2.vhd

二进制数据或者频率信号选择器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux_2 is 
	port(
	sel: in std_logic;
	clk1: in std_logic;
	clk2: in std_logic;
	clko: out std_logic);
end mux_2;

architecture mux_2_arch of mux_2 is 

begin

process(sel)
begin
if sel='1' then
	clko<=clk1;
else 
	clko<=clk2;
end if;
end process;
end mux_2_arch;