eclock.txt

MAXPULS II 下VHDL实现多功能电子钟的源代码

library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024
port(clk: in std_logic;
     f1hz: out std_logic);
end component;

component count60
port(carry: in std_logic;
     rst: in std_logic;
times:out integer range 0 to 59;
full:out std_logic);
end component;

component count24
port(carry: in std_logic;
     rst: in std_logic;
times:out integer range 0 to 23;
full:out std_logic);
end component;

component alarm_set
port(rst,hz1: in std_logic;
alarm,ok: in std_logic;
sec_tune: in std_logic;
min_tune: in std_logic;
hour_tune: in std_logic;
sec,min: out integer range 0 to 59;
hour:out integer range 0 to 23);

end component;

component stop_watch
port(rst,hz1:  in std_logic;
     stop:  in std_logic;
     ok: in std_logic;
     sec_tune: in std_logic;
     min_tune: in std_logic;
     hour_tune: in std_logic;
     index:out std_logic;
     disp:out std_logic;
     stop_sec,stop_min: out integer range 0 to 59;
     stop_hour: out integer range 0 to 23);
end component;

component i60bcd
port(interg: in integer range 0 to 59;
      ten: out std_logic_vector(3 downto 0);
      one: out std_logic_vector(3 downto 0));
end component;

component i24bcd
port(interg: in integer range 0 to 23;
      ten: out std_logic_vector(3 downto 0);
      one: out std_logic_vector(3 downto 0));
end component;

component scan4
port(rst,clk: in std_logic;
     a,b,c,d: in std_logic_vector(6 downto 0);
     pa,pb,pc,pd: out std_logic; 
     mux_out: out std_logic_vector(6 downto 0));
end component;

component scan2
port(rst,clk: in std_logic;
     a,b: in std_logic_vector(6 downto 0);
     pa,pb: out std_logic; 
     mux_out: out std_logic_vector(6 downto 0));
end component;
component bin2led
port(bin : in   std_logic_vector(3 downto 0);
     led : out  std_logic_vector(6 downto 0));
end component; 
end my_pkg;


--div1024
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity div1024 is 
port(clk: in std_logic;
f1hz: out std_logic);
end;
architecture arch of div1024 is
signal count:integer range 0 to 1023;
begin
process(clk)
begin
if rising_edge(clk) then
count<=count+1;
if count<=1023 then f1hz<='1';
   else f1hz<='0';
end if;
end if;
end process;
end arch;
--count60
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count60 is
 port(carry:in std_logic;
      rst:in std_logic;
      times:out integer range 0 to 59;
      full:out std_logic);
end count60;
architecture arch of count60 is

 signal time:integer range 1 to 59;
begin
  process(rst,carry)
  begin
    if rst='1' then time<=0;full<='0';
    elsif rising_edge(carry) then
             if time=59 then time<=0;
                             full<='1';
                  else time<=time+1;
                       full<='0';
             end if;
   end if;
 end process;
 times<=time;
end arch;     
--count24
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity count24 is
  port (carry:in std_logic;
        rst: in std_logic;
        times: out integer range 0 to 23;
        full: out std_logic);
end count24;
architecture arch of count24 is
  signal time:integer range 0 to 23;
begin  
   process(rst,carry)
   begin
     if rst='1' then time<=0; full<='0';
     elsif rising_edge(carry) then
            if time=23  then  time<=0;
                        full<='1';
                        else time<=time+1;
                              full<='0';
             end if;
      end if;
  end process;
  times<=time;
end arch;
--alarm_set
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity alarm_set is
port(rst,hz1: in std_logic;
alarm,ok: in std_logic;
sec_tune: in std_logic;
min_tune: in std_logic;
hour_tune: in std_logic;
sec,min: out integer range 0 to 59;
hour:out integer range 0 to 23);
end;
architecture arch of alarm_set is
 signal sec_tmp,min_tmp: integer range 0 to 59;
 signal hour_tmp: integer range 0 to 23;
begin
tuning : process(rst,hz1,alarm,ok)
begin
if rst='1' then sec_tmp<=0;min_tmp<=0;hour_tmp<=0;
elsif rising_edge(hz1) then
  if alarm='1' and ok='0' then
     if sec_tune='1' then
       if sec_tmp=59 then sec_tmp<=0;  
          else  sec_tmp<=sec_tmp+1;
      end if;
      end if;
     if min_tune='1' then
       if min_tmp=59 then min_tmp<=0;
      else  min_tmp<=min_tmp+1;
    end if;
    end if;
if hour_tune='1' then
 if hour_tmp=23 then hour_tmp<=0;
  else hour_tmp<=hour_tmp+1;
 end if;
end if;
else
null;
end if;
end if;
end process tuning;
sec<=sec_tmp;
min<=min_tmp;
hour<=hour_tmp;
end arch;
--stop_watch 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity stop_watch is
port(rst,hz1:  in std_logic;
     stop:  in std_logic;
     ok: in std_logic;
     sec_tune: in std_logic;
     min_tune: in std_logic;
     hour_tune: in std_logic;
     stop_sec,stop_min: out integer range 0 to 59;
     stop_hour: out integer range 0 to 23;
     index:out std_logic;
     disp:out std_logic);
end stop_watch;
architecture arch of stop_watch is
signal a_sec,a_min:integer range 0 to 59;
signal a_hour: integer range 0 to 23;
begin
process(stop,ok,hz1)
begin
if rst='1' then index<='0';disp<='0';
elsif rising_edge(hz1) then
if stop='1' and ok='0' then 
if sec_tune='1' then
if a_sec=59 then a_sec<=0;
else a_sec<=a_sec+1;
end if;
end if;
if min_tune='1' then
if a_min=59 then a_min<=0;
else a_min<=a_min+1;
end if;
end if;
disp<='1';
elsif stop='1' and ok='1' then
if a_sec=0 then
 if a_min=0 then
  if a_hour=0 then index<='1';
                   disp<='0';
else a_hour<=a_hour-1;
a_min<=59;
a_sec<=59;
end if;
else a_min<=a_min-1;
a_sec<=59;
end if;
else a_sec<=a_sec-1;
index<='0';
disp<='1';
end if;
else disp<='0';
end if;
end if;
end process;
stop_sec<=a_sec;
stop_min<=a_min;
stop_hour<=a_hour;
end arch;
--i60bcd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity i60bcd is
port(interg: in integer range 0 to 59;
      ten: out std_logic_vector(3 downto 0);
      one: out std_logic_vector(3 downto 0));
end i60bcd;
architecture arch of i60bcd is 
begin
process(interg)
begin
case interg is
when 0|10|20|30|40|50=>one<="0000";
when 1|11|21|31|41|51=>one<="0001";
when 2|12|22|32|42|52=>one<="0010";
when 3|13|23|33|43|53=>one<="0011";
when 4|14|24|34|44|54=>one<="0100";
when 5|15|25|35|45|55=>one<="0101";
when 6|16|26|36|46|56=>one<="0110";
when 7|17|27|37|47|57=>one<="0111";
when 8|18|28|38|48|58=>one<="1000";
when 9|19|29|39|49|59=>one<="1001";
end case;
case interg is
when 0|1|2|3|4|5|6|7|8|9=>ten<="0000";
when 10|11|12|13|14|15|16|17|18|19=>ten<="0001";
when 20|21|22|23|24|25|26|27|28|29=>ten<="0010";
when 30|31|32|33|34|35|36|37|38|39=>ten<="0011";
when 40|41|42|43|44|45|46|47|48|49=>ten<="0100";
when 50|51|52|53|54|55|56|57|58|59=>ten<="0101";
when others=>ten<="1110";
end case;
end process;
end arch;
--i24bcd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity i24bcd is
port(interg: in integer range 0 to 23;
      ten: out std_logic_vector(3 downto 0);
      one: out std_logic_vector(3 downto 0));
end i24bcd;
architecture arch of i24bcd is 
begin
process(interg)
begin
case interg is
when 0|10|20=>one<="0000";
when 1|11|21=>one<="0001";
when 2|12|22=>one<="0010";
when 3|13|23=>one<="0011";
when 4|14=>one<="0100";
when 5|15=>one<="0101";
when 6|16=>one<="0110";
when 7|17=>one<="0111";
when 8|18=>one<="1000";
when 9|19=>one<="1001";
when others=>one<="1110";
end case;
case interg is
when 0|1|2|3|4|5|6|7|8|9=>ten<="0000";
when 10|11|12|13|14|15|16|17|18|19=>ten<="0001";
when 20|21|22|23=>ten<="0010";
when others=>ten<="1110";
end case;
end process;
end arch;
--bin2led
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity bin2led is
port(bin : in   std_logic_vector(3 downto 0);
     led : out  std_logic_vector(6 downto 0));
end bin2led;
architecture arch of bin2led IS
begin
with bin select
led<= "1111001" when "0001",
      "0100100" when "0010", 
      "0110000" when "0011",
      "0011001" when "0100",
      "0010010"	when "0101",
      "0000010" when "0110",
      "1111000" when "0111",
      "0000000" when "1000",
      "0010000" when "1001",
      "1000000" when "0000",
      "0000110" when others;
end arch; 
--scan4
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity scan4 is
port(rst,clk: in std_logic;
     a,b,c,d: in std_logic_vector(6 downto 0);
     pa,pb,pc,pd: out std_logic; 
     mux_out: out std_logic_vector(6 downto 0));
end scan4;
architecture arch of scan4 is
signal sel: std_logic_vector(1 downto 0);
begin
process(rst,clk,a,b,c,d)
begin
if rst='1' then sel<="00";
elsif rising_edge(clk) then
sel<=sel+"01";
case sel is
when "00"=>mux_out<=a;
pa<='1';pb<='0';pc<='0';pd<='0';
when "01"=>mux_out<=b;
pa<='0';pb<='1';pc<='0';pd<='0';
when "10"=>mux_out<=c;
pa<='0';pb<='0';pc<='1';pd<='0';
when "11"=>mux_out<=d;
pa<='1';pb<='0';pc<='0';pd<='1';
when others=>mux_out<="101111";
end case;
end if;
end process;
end arch;
--scan2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity scan2 is
port(rst,clk: in std_logic;
     a,b: in std_logic_vector(6 downto 0);
     pa,pb: out std_logic; 
     mux_out: out std_logic_vector(6 downto 0));
end scan2;
architecture arch of scan2 is
signal sel: std_logic_vector(1 downto 0);
begin
process(rst,clk,a,b)
begin
if rst='1' then sel<="00";
elsif rising_edge(clk) then
sel<=sel+"01";
case sel is
when "00"=>mux_out<=a;
pa<='1';pb<='0';
when "01"=>pa<='0';pb<='0';
when "10"=>mux_out<=b;
pa<='0';pb<='1';
when "11"=>pa<='0';pb<='0';
when others=>mux_out<="1011111";
end case;
end if;
end process;
end arch;
--entity
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.my_pkg.all;
entity clock is
port(rst: in std_logic;
clk: in std_logic;
alarm: std_logic;
stop:in std_logic;
ok: in std_logic;
sec_tune: in std_logic;
     min_tune: in std_logic;
     hour_tune: in std_logic;
     led_alarm: out std_logic;
     led_stop: out std_logic;
    seg4: out std_logic_vector(6 downto 0);
p1,p2,p3,p4: out std_logic;
seg2: out std_logic_vector(6 downto 0);
p5,p6: out std_logic);
end clock;  
--architecture
architecture arch of clock is
signal hz1:std_logic;
signal n_sec,n_min: integer range 0 to 59;
signal n_hour: integer range 0 to 23;
signal a_sec,a_min: integer range 0 to 59;
signal a_hour: integer range 0 to 23;
signal s_sec,s_min: integer range 0 to 59;
signal s_hour: integer range 0 to 23;
signal second,minute: integer range 0 to 59;
signal hour: integer range 0 to 23;
signal sec_one,sec_ten,min_one,min_ten:
 std_logic_vector(3 downto 0);
signal  hour_one,hour_ten:
 std_logic_vector(3 downto 0);
signal sec7_one,sec7_ten,min7_one,min7_ten:
 std_logic_vector(6 downto 0);
signal hour7_one,hour7_ten: 
std_logic_vector(6 downto 0);
signal stop_index,alarm_index: std_logic;
signal alarm_disp,stop_disp: std_logic;
begin

--normal_counting block
normal_counting :block
signal full_sec: std_logic;
signal full_min: std_logic;
signal full_hour:std_logic;
begin
u0:div1024 port 
map(clk=>clk,f1hz=>hz1);
u1:count60 port
map(rst=>rst,carry=>hz1,times=>n_sec,full=>full_sec);
u2:count60 port 
map(rst=>rst,carry=>hz1,times=>n_min,full=>full_min);
u3:count24 port
map(rst=>rst,carry=>hz1,times=>n_hour,full=>full_hour);
end block normal_counting;
--stop_wrtch block
stop_w:block
begin 
u4:stop_watch port
map(rst=>rst,hz1=>hz1,stop=>stop,ok=>ok,sec_tune=>sec_tune,min_tune=>min_tune,hour_tune=>hour_tune,
stop_sec=>s_sec,stop_min=>s_min,stop_hour=>s_hour,index=>stop_index,disp=>stop_disp);
p1:process(rst,stop_index)
begin
if rst='1' then led_stop<='0';
elsif rising_edge(stop_index) then
led_stop<='1';
end if;
end process p1;
end block stop_w;


--alarm seting
alarm_setting:block
begin
u5:alarm_set port
map(rst=>rst,hz1=>hz1,alarm=>alarm,ok=>ok,min_tune=>min_tune,sec_tune=>sec_tune,
hour_tune=>hour_tune,sec=>a_sec,min=>a_min,hour=>a_hour);
p1:process(alarm,ok)
begin
if rst='1' then alarm_index<='0';
elsif  alarm='1' and ok='1' then
if(a_sec=n_sec and a_min=n_min and a_hour=n_hour)
then alarm_index<='1';
else alarm_index<='0';
end if;
end if;
alarm_disp<=(alarm and not ok) and not alarm_index;
end process p1;
 p2:process(rst,alarm_index)
begin
if rst='1' then led_alarm<='0';
elsif rising_edge(alarm_index) then
led_alarm<='1';
end if;

end process p2;
end block alarm_setting;

--output
output:block
begin
process(clk,stop_disp,alarm_disp)
begin
if rising_edge(clk) then
if stop_disp='1' then second<=s_sec;
minute<=s_min;
hour<=s_hour;
elsif alarm_disp='1' then second<=a_sec;
minute<=a_min;
hour<=a_hour;
else second<=n_sec;
minute<=n_min;
hour<=n_hour;
end if;
end if;
end process;
u6:i60bcd port
map(interg=>second,ten=>sec_ten,one=>sec_one);
u7:i60bcd port
map(interg=>minute,ten=>min_ten,one=>min_one);
u8:i24bcd port
map(interg=>hour,ten=>hour_ten,one=>hour_one);
end block output;
--scan_display
scan_display:block
begin
u11:bin2led port map(bin=>sec_one,led=>sec7_one);
u12:bin2led port map(bin=>sec_ten,led=>sec7_ten);
u13:bin2led port map(bin=>min_one,led=>min7_one);
u14:bin2led port map(bin=>min_ten,led=>min7_ten);
u15:bin2led port map(bin=>hour_one,led=>hour7_one);
u16:bin2led port map(bin=>hour_ten,led=>hour7_one);
u17:scan4 port map(rst=>rst,clk=>clk,a=>sec7_one,b=>sec7_ten,
c=>min7_one,d=>min7_ten,mux_out=>seg4,pa=>p1,pb=>p2,pc=>p3,pd=>p4);
u18:scan2 port map(rst=>rst,clk=>clk,a=>hour7_one,b=>hour7_ten,
mux_out=>seg2,pa=>p5,pb=>p6);
end block scan_display;