qep_data_bus.v

来自「基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL」· Verilog 代码 · 共 94 行

//`include "qep4.v"
//`include "cnt_pulse.v"
//`include "data_bus.v"
module qep_data_bus(data_inout,addr_in,rst_in,clk_input,
					clr0_in,clr1_in,a_in,b_in,f_in,d_in,
					ale_in,read_in,write_in,ram_cs_out,
					led_out,ledsl_out,ledout_out,clk_out);
//module data_bus(data_inout,cs_out,a0_out,ram_cs_out,data_out,write_in,read_in
//		,ale_in,clk_in,addr_in,rst_in,data_in);

//module cnt_pulse(cnt_out,fin_in,din_in,clk_in,en_in,clr_in,a0_in);

//module  qep4 (qep_out,a_in,b_in,clk_in,clr_in,en_in,a0_in);
//module  disp (ledout_out,ledsl_out,led_out,clr_in,clk_in,cs_in,data_in,a0_in);

inout	[7:0]	data_inout;
input	[15:0]	addr_in;
input	clk_input,ale_in,read_in,write_in,rst_in;

output	clk_out;
output	ram_cs_out;
output	[7:0]	ledout_out;
output	[3:0]	ledsl_out;
output	led_out;
//output	[7:0]	data_out;
input	[5:0]	a_in;
input	[5:0]	b_in;
input	clr0_in;

input	[5:0]	f_in;
input	[5:0]	d_in;
input	clr1_in;

wire	[15:0]	cs_out;
wire	a0;
tri		[7:0]	data;
wire	clk_in;
wire	[7:0]	data_write;
assign	clk_out=clk_input;
//clk_gen		t_clk_gen (.clk_in(clk_input),.en_in(rst_in),.clk_out(clk_in));
data_bus	t_data_bus(.data_inout(data_inout),.cs_out(cs_out),.a0_out(a0),
					   .ram_cs_out(ram_cs_out),.data_putout(data_write),.write_in(write_in),
					   .read_in(read_in),.ale_in(ale_in),.clk_in(clk_input),.add_in(addr_in),
					   .rst_in(rst_in),.data_in(data));

disp		t_disp 	   (.ledout_out(ledout_out),.ledsl_out(ledsl_out),.led_out(led_out),
						.clr_in(rst_in),.clk_in(clk_input),.cs_in(cs_out[14]),
						.data_in(data_write),.a0_in(a0));


qep4		t_qep4_0  (.qep_out(data),.a_in(a_in[0]),.b_in(b_in[0]),.clk_in(clk_input),
					   .clr_in(clr0_in),.en_in(cs_out[0]),.a0_in(a0));

qep4		t_qep4_1  (.qep_out(data),.a_in(a_in[1]),.b_in(b_in[1]),.clk_in(clk_input),
					   .clr_in(clr0_in),.en_in(cs_out[1]),.a0_in(a0));

qep4		t_qep4_2  (.qep_out(data),.a_in(a_in[2]),.b_in(b_in[2]),.clk_in(clk_input),
					   .clr_in(clr0_in),.en_in(cs_out[2]),.a0_in(a0));

qep4		t_qep4_3  (.qep_out(data),.a_in(a_in[3]),.b_in(b_in[3]),.clk_in(clk_input),
					   .clr_in(clr0_in),.en_in(cs_out[3]),.a0_in(a0));

qep4		t_qep4_4  (.qep_out(data),.a_in(a_in[4]),.b_in(b_in[4]),.clk_in(clk_input),
					   .clr_in(clr0_in),.en_in(cs_out[4]),.a0_in(a0));

qep4		t_qep4_5  (.qep_out(data),.a_in(a_in[5]),.b_in(b_in[5]),.clk_in(clk_input),
					   .clr_in(clr0_in),.en_in(cs_out[5]),.a0_in(a0));


cnt_pulse	t_cnt_pulse_0(.cnt_out(data),.fin_in(f_in[0]),.din_in(d_in[0]),.clk_in(clk_input),
						  .en_in(cs_out[8]),.clr_in(clr1_in),.a0_in(a0));

cnt_pulse	t_cnt_pulse_1(.cnt_out(data),.fin_in(f_in[1]),.din_in(d_in[1]),.clk_in(clk_input),
						  .en_in(cs_out[9]),.clr_in(clr1_in),.a0_in(a0));

cnt_pulse	t_cnt_pulse_2(.cnt_out(data),.fin_in(f_in[2]),.din_in(d_in[2]),.clk_in(clk_input),
						  .en_in(cs_out[10]),.clr_in(clr1_in),.a0_in(a0));

cnt_pulse	t_cnt_pulse_3(.cnt_out(data),.fin_in(f_in[3]),.din_in(d_in[3]),.clk_in(clk_input),
						  .en_in(cs_out[11]),.clr_in(clr1_in),.a0_in(a0));

cnt_pulse	t_cnt_pulse_4(.cnt_out(data),.fin_in(f_in[4]),.din_in(d_in[4]),.clk_in(clk_input),
						  .en_in(cs_out[12]),.clr_in(clr1_in),.a0_in(a0));

cnt_pulse	t_cnt_pulse_5(.cnt_out(data),.fin_in(f_in[5]),.din_in(d_in[5]),.clk_in(clk_input),
						  .en_in(cs_out[13]),.clr_in(clr1_in),.a0_in(a0));



endmodule