leospec.log

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

Info: Finished reading design
FALSE
qep_data_bus.edf
-- Run Started On Sun Dec 11 21:16:09 中国标准时间 2005
--
Info: setting modgen_select to small
-- optimize -target flex10a -effort quick -chip -area -hierarchy=auto
Info, New design data_bus_notri was created after pushing boundarytristates up from data_bus.
Info, All references of data_bus have been changed.
Info, New design qep4_notri was created after pushing boundarytristates up from qep4.
Info, All references of qep4 have been changed.
Info, New design cnt_pulse_notri was created after pushing boundarytristates up from cnt_pulse.
Info, All references of cnt_pulse have been changed.
Using default wire table: STD-1
Info, Instances dissolved by autodissolve in View .work.qep_data_bus.INTERFACE
"F:/Verilog_Pro/qep_data_bus/qep_data_bus.v", line 62: t_cnt_pulse_0_notri (cnt_pulse_notri)
"F:/Verilog_Pro/qep_data_bus/qep_data_bus.v", line 65: t_cnt_pulse_1_notri (cnt_pulse_notri)
"F:/Verilog_Pro/qep_data_bus/qep_data_bus.v", line 68: t_cnt_pulse_2_notri (cnt_pulse_notri)
"F:/Verilog_Pro/qep_data_bus/qep_data_bus.v", line 71: t_cnt_pulse_3_notri (cnt_pulse_notri)
"F:/Verilog_Pro/qep_data_bus/qep_data_bus.v", line 74: t_cnt_pulse_4_notri (cnt_pulse_notri)
"F:/Verilog_Pro/qep_data_bus/qep_data_bus.v", line 77: t_cnt_pulse_5_notri (cnt_pulse_notri)
-- Start optimization for design .work.disp.INTERFACE_unfold_1818
Using default wire table: STD-1
              est est                                 
      Pass    LCs Delay DFFs TRIs  PIs POs    --CPU--
                                                min:sec
      1        93     18   19    0   12  13      00:01 
Info: setting opt_best_result to 1675.860000
Info: setting opt_best_pass to 0
-- Start optimization for design .work.data_bus_notri.INTERFACE_unfold_2093
Using default wire table: STD-1
              est est                                 
      Pass    LCs Delay DFFs TRIs  PIs POs    --CPU--
                                                min:sec
      1        99     13   35    0   27  33      00:01 
Info: setting opt_best_result to 1314.720000
Info: setting opt_best_pass to 0
-- Start optimization for design .work.qep4_notri.INTERFACE
Using default wire table: STD-1
              est est                                 
      Pass    LCs Delay DFFs TRIs  PIs POs    --CPU--
                                                min:sec
      1        59     16   31    0    6   8      00:00 
Info: setting opt_best_result to 942.820000
Info: setting opt_best_pass to 0
-- Start optimization for design .work.qep_data_bus.INTERFACE
Using default wire table: STD-1
Warning : Tristate at a0 replaced by AND Gate.
              est est                                 
      Pass    LCs Delay DFFs TRIs  PIs POs    --CPU--
                                                min:sec
      1       297      8   84    8   37  22      00:01 
Info: setting opt_best_result to 2349.270000
Info: setting opt_best_pass to 0
Info: setting optimize_timing_cpu_limit to 182
Using default wire table: STD-1
-- Start timing optimization for design .work.disp.INTERFACE_unfold_1818
Starting Timing Characterization...
Starting Timing Analysis...
Using default wire table: STD-1
Timing analysis done, time = 1 CPU secs.
Timing characterization done, time = 1 CPU secs.
Info: setting optimize_timing_cpu_limit to 0
Info: setting modgen_select to auto

*******************************************************

Cell: qep_data_bus    View: INTERFACE    Library: work

*******************************************************

 Number of ports :                      69
 Number of nets :                      602
 Number of instances :                 390
 Number of references to this view :     0

Total accumulated area : 
 Number of CARRYs :                    210
 Number of CASCADEs :                  208
 Number of DFFs :                      324
 Number of LCs :                       843
 Number of TRIs :                        8
 Number of VCC :                         9
 Number of accumulated instances :    1333
***********************************************
Device Utilization for EPF10K30ATC144
***********************************************
Resource                Used    Avail   Utilization
-----------------------------------------------
IOs                     69      102      67.65%
LCs                     843     1728     48.78%
DFFs                    324     1968     16.46%
Memory Bits             0       12288     0.00%
CARRYs                  210     1728     12.15%
CASCADEs                208     1728     12.04%

-----------------------------------------------
                        Clock Frequency Report

	Clock                : Frequency
      ------------------------------------

	clk_in               : 50.7 MHz
	t_cnt_pulse_0_notri_NOT_clk_in : 74.8 MHz
	t_disp/NOT_clk_in    : 85.5 MHz
	t_qep4_0_notri/NOT_clk_in : 85.5 MHz
	t_qep4_1_notri/NOT_clk_in : 77.3 MHz
	t_qep4_2_notri/NOT_clk_in : 77.3 MHz
	t_qep4_3_notri/NOT_clk_in : 77.3 MHz
	t_qep4_4_notri/NOT_clk_in : 85.5 MHz
	t_qep4_5_notri/NOT_clk_in : 85.5 MHz

                        Critical Path Report

Critical path #1, (unconstrained path)
NAME                                                     GATE              ARRIVAL              LOAD
----------------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network                                                   0.00 (ideal)


t_data_bus_notri/reg_add_reg(2)/Q                        DFF         0.00  3.44 up             3.33
t_data_bus_notri/nx204/O                                 F2_CAS      1.50  4.94 up             2.63
cs_out(1)/O                                              F4_LUT      3.84  8.78 up             3.24
nx844/O                                                  F4_LUT      2.50  11.28 up             1.90
nx776/O                                                  CASCADE2    0.90  12.18 up             1.90
nx846/O                                                  F3_LUT      2.50  14.68 up             1.90
nx732/O                                                  CASCADE2    0.90  15.58 up             1.90
data_in(3)/O                                             F1_LUT      0.00  15.58 up             1.90
t_data_bus_notri/nx235/O                                 F3_LUT      2.50  18.08 up             1.90
t_data_bus_notri/reg_data_out_reg(3)/D                   DFF         0.00  18.08 up             0.00
data arrival time                                                          18.08


data required time                                                      not specified
----------------------------------------------------------------------------------------------------
data required time                                                      not specified
data arrival time                                                          18.08
                                                                        ----------
                                                                     unconstrained path
----------------------------------------------------------------------------------------------------



Info, Timing estimates are preliminary
Info, Altera place and route software needs to be run to obtain accurate timing results
-- Design summary in file 'qep_data_bus.sum'
AutoWrite args are : qep_data_bus.edf
-- Applying renaming rule 'ALTERA' to database
Warning, Renaming will cause your database to change
-- Calling set_altera_eqn to set up writing Equations
-- Writing file qep_data_bus.edf
Info, Writing batch file 'qep_data_bus.tcl'
Info: setting quartus_exec_path to D:\altera\quartus50/bin
-- CPU time taken for this run was  35.64 sec
-- Run Successfully Ended On  Sun Dec 11 21:16:46 中国标准时间 2005
0
Info: Finished Synthesis run