📄 qep_data_bus.sim.vwf

📁 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的
💻 VWF
📖 第 1 页 / 共 5 页
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		{
			REPEAT = 2;
			LEVEL 1 FOR 16000.0;
			LEVEL 0 FOR 16000.0;
		}
		LEVEL 1 FOR 16000.0;
		LEVEL 0 FOR 3709.8;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 8290.2;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 8000.0;
			LEVEL 0 FOR 8000.0;
		}
		LEVEL 1 FOR 8000.0;
		LEVEL 0 FOR 3709.8;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4290.2;
		NODE
		{
			REPEAT = 11;
			LEVEL 1 FOR 4000.0;
			LEVEL 0 FOR 4000.0;
		}
		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 3709.8;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2290.2;
		NODE
		{
			REPEAT = 24;
			LEVEL 1 FOR 2000.0;
			LEVEL 0 FOR 2000.0;
		}
		LEVEL 1 FOR 1709.8;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1290.2;
		NODE
		{
			REPEAT = 49;
			LEVEL 1 FOR 1000.0;
			LEVEL 0 FOR 1000.0;
		}
		LEVEL 1 FOR 709.8;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 790.2;
		NODE
		{
			REPEAT = 99;
			LEVEL 1 FOR 500.0;
			LEVEL 0 FOR 500.0;
		}
		LEVEL 1 FOR 209.8;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 540.2;
		NODE
		{
			REPEAT = 198;
			LEVEL 1 FOR 250.0;
			LEVEL 0 FOR 250.0;
		}
		LEVEL 1 FOR 250.0;
		LEVEL 0 FOR 209.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 90615.2;
		LEVEL 1 FOR 9384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73615.2;
		LEVEL 1 FOR 26384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 90615.2;
		LEVEL 1 FOR 9384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73615.2;
		LEVEL 1 FOR 26384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 88615.2;
		LEVEL 1 FOR 11384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 81115.2;
		LEVEL 1 FOR 7500.0;
		LEVEL 0 FOR 11384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 88615.2;
		LEVEL 1 FOR 11384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 81115.2;
		LEVEL 1 FOR 7500.0;
		LEVEL 0 FOR 11384.8;
	}
}

TRANSITION_LIST("disp:t_disp|data[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|link_data_wr")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73540.2;
		LEVEL 1 FOR 2025.0;
		LEVEL 0 FOR 5475.0;
		LEVEL 1 FOR 3025.0;
		LEVEL 0 FOR 4475.0;
		LEVEL 1 FOR 525.0;
		LEVEL 0 FOR 1475.0;
		LEVEL 1 FOR 525.0;
		LEVEL 0 FOR 3975.0;
		LEVEL 1 FOR 525.0;
		LEVEL 0 FOR 4434.8;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 71508.3;
		LEVEL 1 FOR 20500.0;
		LEVEL 0 FOR 7991.7;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 71508.4;
		LEVEL 1 FOR 20500.0;
		LEVEL 0 FOR 7991.6;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 9008.2;
		LEVEL 1 FOR 19000.0;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9000.0;
		LEVEL 0 FOR 14500.0;
		LEVEL 1 FOR 8500.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2000.0;
		LEVEL 0 FOR 7991.8;
	}
}

TRANSITION_LIST("clk_input")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 4000;
			LEVEL 0 FOR 12.5;
			LEVEL 1 FOR 12.5;
		}
	}
}

TRANSITION_LIST("clk_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 22.3;
		NODE
		{
			REPEAT = 3999;
			LEVEL 1 FOR 12.5;
			LEVEL 0 FOR 12.5;
		}
		LEVEL 1 FOR 2.7;
	}
}

TRANSITION_LIST("led_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1014.0;
		LEVEL 0 FOR 98986.0;
	}
}

TRANSITION_LIST("ledsl_out[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1016.1;
		LEVEL 0 FOR 72535.8;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 25.0;
			LEVEL 0 FOR 7475.0;
		}
		LEVEL 1 FOR 25.0;
		LEVEL 0 FOR 1975.0;
		LEVEL 1 FOR 25.0;
		LEVEL 0 FOR 9423.1;
	}
}

TRANSITION_LIST("ledsl_out[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 100000.0;
	}
}

TRANSITION_LIST("ledsl_out[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 100000.0;
	}
}

TRANSITION_LIST("ledsl_out[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 100000.0;
	}
}

TRANSITION_LIST("ledout_out[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73628.7;
		LEVEL 1 FOR 16998.8;
		LEVEL 0 FOR 9372.5;
	}
}

TRANSITION_LIST("ledout_out[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("ledout_out[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("ledout_out[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73626.5;
		LEVEL 1 FOR 17001.0;
		LEVEL 0 FOR 9372.5;
	}
}

TRANSITION_LIST("ledout_out[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73625.4;
		LEVEL 1 FOR 26374.6;
	}
}

TRANSITION_LIST("ledout_out[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 73625.4;
		LEVEL 1 FOR 26374.6;
	}
}

TRANSITION_LIST("ledout_out[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 90626.4;
		LEVEL 0 FOR 9373.6;
	}
}

TRANSITION_LIST("ledout_out[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 100000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk_input";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk_out";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "a_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "b_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clr0_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "f_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "d_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clr1_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 8;
	TREE_LEVEL = 0;
	CHILDREN = 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "read_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "ale_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data_bus:t_data_bus|link_data_wr";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 27;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data_bus:t_data_bus|add_reg";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 28;
	TREE_LEVEL = 0;
	CHILDREN = 29, 30, 31, 32;
}

DISPLAY_LINE
{
	CHANNEL = "data_bus:t_data_bus|add_reg[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 28;
}

DISPLAY_LINE
{
	CHANNEL = "data_bus:t_data_bus|add_reg[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 28;
}
💿 文件大小 1161 K
👤 上传用户 zergwyk
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#Verilog #FPGA #HDL #接口
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