qep_data_bus.map.qmsg

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_pulse cnt_pulse:t_cnt_pulse_0 " "Info: Elaborating entity \"cnt_pulse\" for hierarchy \"cnt_pulse:t_cnt_pulse_0\"" {  } { { "qep_data_bus.v" "t_cnt_pulse_0" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 71 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "13 " "Info: Inferred 13 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "disp:t_disp\|cnt_clk\[0\]~24 24 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: \"disp:t_disp\|cnt_clk\[0\]~24\"" {  } { { "disp.v" "cnt_clk\[0\]~24" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/disp.v" 16 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_pulse:t_cnt_pulse_5\|cnt_reg\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_pulse:t_cnt_pulse_5\|cnt_reg\[0\]~48\"" {  } { { "cnt_pulse.v" "cnt_reg\[0\]~48" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 4 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_pulse:t_cnt_pulse_4\|cnt_reg\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_pulse:t_cnt_pulse_4\|cnt_reg\[0\]~48\"" {  } { { "cnt_pulse.v" "cnt_reg\[0\]~48" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 4 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_pulse:t_cnt_pulse_3\|cnt_reg\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_pulse:t_cnt_pulse_3\|cnt_reg\[0\]~48\"" {  } { { "cnt_pulse.v" "cnt_reg\[0\]~48" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 4 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_pulse:t_cnt_pulse_2\|cnt_reg\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_pulse:t_cnt_pulse_2\|cnt_reg\[0\]~48\"" {  } { { "cnt_pulse.v" "cnt_reg\[0\]~48" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 4 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_pulse:t_cnt_pulse_1\|cnt_reg\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_pulse:t_cnt_pulse_1\|cnt_reg\[0\]~48\"" {  } { { "cnt_pulse.v" "cnt_reg\[0\]~48" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 4 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_pulse:t_cnt_pulse_0\|cnt_reg\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_pulse:t_cnt_pulse_0\|cnt_reg\[0\]~48\"" {  } { { "cnt_pulse.v" "cnt_reg\[0\]~48" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 4 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "qep4:t_qep4_0\|qep_reg\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"qep4:t_qep4_0\|qep_reg\[0\]~16\"" {  } { { "qep4.v" "qep_reg\[0\]~16" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 10 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "qep4:t_qep4_1\|qep_reg\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"qep4:t_qep4_1\|qep_reg\[0\]~16\"" {  } { { "qep4.v" "qep_reg\[0\]~16" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 10 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "qep4:t_qep4_2\|qep_reg\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"qep4:t_qep4_2\|qep_reg\[0\]~16\"" {  } { { "qep4.v" "qep_reg\[0\]~16" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 10 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "qep4:t_qep4_3\|qep_reg\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"qep4:t_qep4_3\|qep_reg\[0\]~16\"" {  } { { "qep4.v" "qep_reg\[0\]~16" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 10 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "qep4:t_qep4_4\|qep_reg\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"qep4:t_qep4_4\|qep_reg\[0\]~16\"" {  } { { "qep4.v" "qep_reg\[0\]~16" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 10 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "qep4:t_qep4_5\|qep_reg\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"qep4:t_qep4_5\|qep_reg\[0\]~16\"" {  } { { "qep4.v" "qep_reg\[0\]~16" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_pulse:t_cnt_pulse_4\|a0_reg cnt_pulse:t_cnt_pulse_5\|a0_reg " "Info: Duplicate register \"cnt_pulse:t_cnt_pulse_4\|a0_reg\" merged to single register \"cnt_pulse:t_cnt_pulse_5\|a0_reg\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_pulse:t_cnt_pulse_3\|a0_reg cnt_pulse:t_cnt_pulse_5\|a0_reg " "Info: Duplicate register \"cnt_pulse:t_cnt_pulse_3\|a0_reg\" merged to single register \"cnt_pulse:t_cnt_pulse_5\|a0_reg\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_pulse:t_cnt_pulse_2\|a0_reg cnt_pulse:t_cnt_pulse_5\|a0_reg " "Info: Duplicate register \"cnt_pulse:t_cnt_pulse_2\|a0_reg\" merged to single register \"cnt_pulse:t_cnt_pulse_5\|a0_reg\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_pulse:t_cnt_pulse_1\|a0_reg cnt_pulse:t_cnt_pulse_5\|a0_reg " "Info: Duplicate register \"cnt_pulse:t_cnt_pulse_1\|a0_reg\" merged to single register \"cnt_pulse:t_cnt_pulse_5\|a0_reg\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_pulse:t_cnt_pulse_0\|a0_reg cnt_pulse:t_cnt_pulse_5\|a0_reg " "Info: Duplicate register \"cnt_pulse:t_cnt_pulse_0\|a0_reg\" merged to single register \"cnt_pulse:t_cnt_pulse_5\|a0_reg\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "qep4:t_qep4_4\|a0_reg qep4:t_qep4_5\|a0_reg " "Info: Duplicate register \"qep4:t_qep4_4\|a0_reg\" merged to single register \"qep4:t_qep4_5\|a0_reg\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 11 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "qep4:t_qep4_3\|a0_reg qep4:t_qep4_5\|a0_reg " "Info: Duplicate register \"qep4:t_qep4_3\|a0_reg\" merged to single register \"qep4:t_qep4_5\|a0_reg\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 11 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "qep4:t_qep4_2\|a0_reg qep4:t_qep4_5\|a0_reg " "Info: Duplicate register \"qep4:t_qep4_2\|a0_reg\" merged to single register \"qep4:t_qep4_5\|a0_reg\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 11 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "qep4:t_qep4_1\|a0_reg qep4:t_qep4_5\|a0_reg " "Info: Duplicate register \"qep4:t_qep4_1\|a0_reg\" merged to single register \"qep4:t_qep4_5\|a0_reg\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 11 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "qep4:t_qep4_0\|a0_reg qep4:t_qep4_5\|a0_reg " "Info: Duplicate register \"qep4:t_qep4_0\|a0_reg\" merged to single register \"qep4:t_qep4_5\|a0_reg\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 11 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[4\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[4\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[0\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[0\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[1\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[1\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[5\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[5\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[6\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[6\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[2\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[2\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[3\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[3\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "data_bus:t_data_bus\|data_putout\[7\] " "Warning: Converting TRI node \"data_bus:t_data_bus\|data_putout\[7\]\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ledout_out\[7\] VCC " "Warning: Pin \"ledout_out\[7\]\" stuck at VCC" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 22 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "10 " "Warning: Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[5\] " "Warning: No output dependent on input pin \"addr_in\[5\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[6\] " "Warning: No output dependent on input pin \"addr_in\[6\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[7\] " "Warning: No output dependent on input pin \"addr_in\[7\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[8\] " "Warning: No output dependent on input pin \"addr_in\[8\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[9\] " "Warning: No output dependent on input pin \"addr_in\[9\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[10\] " "Warning: No output dependent on input pin \"addr_in\[10\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[11\] " "Warning: No output dependent on input pin \"addr_in\[11\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[12\] " "Warning: No output dependent on input pin \"addr_in\[12\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[13\] " "Warning: No output dependent on input pin \"addr_in\[13\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "addr_in\[14\] " "Warning: No output dependent on input pin \"addr_in\[14\]\"" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "973 " "Info: Implemented 973 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "47 " "Info: Implemented 47 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "903 " "Info: Implemented 903 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 27 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 15 21:16:20 2005 " "Info: Processing ended: Thu Dec 15 21:16:20 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}