qep_data_bus.map.qmsg

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 15 21:16:07 2005 " "Info: Processing started: Thu Dec 15 21:16:07 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qep_data_bus -c qep_data_bus " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qep_data_bus -c qep_data_bus" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Info: Found entity 1: clk_gen" {  } { { "clk_gen.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/clk_gen.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qep_data_bus.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file qep_data_bus.v" { { "Info" "ISGN_ENTITY_NAME" "1 qep_data_bus " "Info: Found entity 1: qep_data_bus" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "cnt_pulse.v(10) " "Warning: (10273) Verilog HDL warning at cnt_pulse.v(10): extended using \"x\" or \"z\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "cnt_pulse.v(56) " "Warning: (10273) Verilog HDL warning at cnt_pulse.v(56): extended using \"x\" or \"z\"" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 56 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_pulse.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt_pulse.v" { { "Info" "ISGN_ENTITY_NAME" "1 cnt_pulse " "Info: Found entity 1: cnt_pulse" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "data_bus.v(37) " "Warning: (10273) Verilog HDL warning at data_bus.v(37): extended using \"x\" or \"z\"" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "data_bus.v(38) " "Warning: (10273) Verilog HDL warning at data_bus.v(38): extended using \"x\" or \"z\"" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 38 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_bus.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_bus.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_bus " "Info: Found entity 1: data_bus" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "disp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file disp.v" { { "Info" "ISGN_ENTITY_NAME" "1 disp " "Info: Found entity 1: disp" {  } { { "disp.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/disp.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "qep4.v(14) " "Warning: (10273) Verilog HDL warning at qep4.v(14): extended using \"x\" or \"z\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "qep4.v(63) " "Warning: (10273) Verilog HDL warning at qep4.v(63): extended using \"x\" or \"z\"" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 63 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qep4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file qep4.v" { { "Info" "ISGN_ENTITY_NAME" "1 qep4 " "Info: Found entity 1: qep4" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qep_data_bus " "Info: Elaborating entity \"qep_data_bus\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk_in qep_data_bus.v(37) " "Info: (10035) Verilog HDL or VHDL information at qep_data_bus.v(37): object \"clk_in\" declared but not used" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 37 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_bus data_bus:t_data_bus " "Info: Elaborating entity \"data_bus\" for hierarchy \"data_bus:t_data_bus\"" {  } { { "qep_data_bus.v" "t_data_bus" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 44 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ram_cs_reg data_bus.v(17) " "Info: (10035) Verilog HDL or VHDL information at data_bus.v(17): object \"ram_cs_reg\" declared but not used" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 17 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "link_add data_bus.v(28) " "Info: (10035) Verilog HDL or VHDL information at data_bus.v(28): object \"link_add\" declared but not used" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 28 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "disp disp:t_disp " "Info: Elaborating entity \"disp\" for hierarchy \"disp:t_disp\"" {  } { { "qep_data_bus.v" "t_disp" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 48 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "qep4 qep4:t_qep4_0 " "Info: Elaborating entity \"qep4\" for hierarchy \"qep4:t_qep4_0\"" {  } { { "qep_data_bus.v" "t_qep4_0" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 52 -1 0 } }  } 0}