qep_data_bus.sim.qmsg

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 15 20:47:58 2005 " "Info: Processing started: Thu Dec 15 20:47:58 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off qep_data_bus -c qep_data_bus " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off qep_data_bus -c qep_data_bus" {  } {  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "disp:t_disp\|a0_reg " "Warning: Ignored node in vector source file. Can't find corresponding node name \"disp:t_disp\|a0_reg\" in design." {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "" { Waveform "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "disp:t_disp\|a0_reg" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "data_bus:t_data_bus\|a0_reg " "Warning: Ignored node in vector source file. Can't find corresponding node name \"data_bus:t_data_bus\|a0_reg\" in design." {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "" { Waveform "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "data_bus:t_data_bus\|a0_reg" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "data_bus:t_data_bus\|link_data " "Warning: Ignored node in vector source file. Can't find corresponding node name \"data_bus:t_data_bus\|link_data\" in design." {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "" { Waveform "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "data_bus:t_data_bus\|link_data" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "data_bus:t_data_bus\|link_add " "Warning: Ignored node in vector source file. Can't find corresponding node name \"data_bus:t_data_bus\|link_add\" in design." {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "" { Waveform "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.vwf" "data_bus:t_data_bus\|link_add" "0 ps" "0 ps" "" } }  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     19.33 % " "Info: Simulation coverage is      19.33 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "65537 " "Info: Number of transitions in simulation is 65537" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 4 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 15 20:48:17 2005 " "Info: Processing ended: Thu Dec 15 20:48:17 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0}  } {  } 0}