qep_data_bus.hier_info

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

|qep_data_bus
data_inout[0] <= data_bus:t_data_bus.data_inout
data_inout[1] <= data_bus:t_data_bus.data_inout
data_inout[2] <= data_bus:t_data_bus.data_inout
data_inout[3] <= data_bus:t_data_bus.data_inout
data_inout[4] <= data_bus:t_data_bus.data_inout
data_inout[5] <= data_bus:t_data_bus.data_inout
data_inout[6] <= data_bus:t_data_bus.data_inout
data_inout[7] <= data_bus:t_data_bus.data_inout
addr_in[0] => addr_in[0]~15.IN1
addr_in[1] => addr_in[1]~14.IN1
addr_in[2] => addr_in[2]~13.IN1
addr_in[3] => addr_in[3]~12.IN1
addr_in[4] => addr_in[4]~11.IN1
addr_in[5] => addr_in[5]~10.IN1
addr_in[6] => addr_in[6]~9.IN1
addr_in[7] => addr_in[7]~8.IN1
addr_in[8] => addr_in[8]~7.IN1
addr_in[9] => addr_in[9]~6.IN1
addr_in[10] => addr_in[10]~5.IN1
addr_in[11] => addr_in[11]~4.IN1
addr_in[12] => addr_in[12]~3.IN1
addr_in[13] => addr_in[13]~2.IN1
addr_in[14] => addr_in[14]~1.IN1
addr_in[15] => addr_in[15]~0.IN1
rst_in => rst_in~0.IN2
clk_input => clk_input~0.IN14
clr0_in => clr0_in~0.IN6
clr1_in => clr1_in~0.IN6
a_in[0] => a_in[0]~5.IN1
a_in[1] => a_in[1]~4.IN1
a_in[2] => a_in[2]~3.IN1
a_in[3] => a_in[3]~2.IN1
a_in[4] => a_in[4]~1.IN1
a_in[5] => a_in[5]~0.IN1
b_in[0] => b_in[0]~5.IN1
b_in[1] => b_in[1]~4.IN1
b_in[2] => b_in[2]~3.IN1
b_in[3] => b_in[3]~2.IN1
b_in[4] => b_in[4]~1.IN1
b_in[5] => b_in[5]~0.IN1
f_in[0] => f_in[0]~5.IN1
f_in[1] => f_in[1]~4.IN1
f_in[2] => f_in[2]~3.IN1
f_in[3] => f_in[3]~2.IN1
f_in[4] => f_in[4]~1.IN1
f_in[5] => f_in[5]~0.IN1
d_in[0] => d_in[0]~5.IN1
d_in[1] => d_in[1]~4.IN1
d_in[2] => d_in[2]~3.IN1
d_in[3] => d_in[3]~2.IN1
d_in[4] => d_in[4]~1.IN1
d_in[5] => d_in[5]~0.IN1
ale_in => ale_in~0.IN1
read_in => read_in~0.IN1
write_in => write_in~0.IN1
ram_cs_out <= data_bus:t_data_bus.ram_cs_out
led_out <= disp:t_disp.led_out
ledsl_out[0] <= disp:t_disp.ledsl_out
ledsl_out[1] <= disp:t_disp.ledsl_out
ledsl_out[2] <= disp:t_disp.ledsl_out
ledsl_out[3] <= disp:t_disp.ledsl_out
ledout_out[0] <= disp:t_disp.ledout_out
ledout_out[1] <= disp:t_disp.ledout_out
ledout_out[2] <= disp:t_disp.ledout_out
ledout_out[3] <= disp:t_disp.ledout_out
ledout_out[4] <= disp:t_disp.ledout_out
ledout_out[5] <= disp:t_disp.ledout_out
ledout_out[6] <= disp:t_disp.ledout_out
ledout_out[7] <= disp:t_disp.ledout_out
clk_out <= clk_input~0.DB_MAX_OUTPUT_PORT_TYPE


|qep_data_bus|data_bus:t_data_bus
data_inout[0] <= data_inout~16
data_inout[1] <= data_inout~15
data_inout[2] <= data_inout~14
data_inout[3] <= data_inout~13
data_inout[4] <= data_inout~12
data_inout[5] <= data_inout~11
data_inout[6] <= data_inout~10
data_inout[7] <= data_inout~9
cs_out[0] <= cs_out~16.DB_MAX_OUTPUT_PORT_TYPE
cs_out[1] <= cs_out~15.DB_MAX_OUTPUT_PORT_TYPE
cs_out[2] <= cs_out~14.DB_MAX_OUTPUT_PORT_TYPE
cs_out[3] <= cs_out~13.DB_MAX_OUTPUT_PORT_TYPE
cs_out[4] <= cs_out~12.DB_MAX_OUTPUT_PORT_TYPE
cs_out[5] <= cs_out~11.DB_MAX_OUTPUT_PORT_TYPE
cs_out[6] <= cs_out~10.DB_MAX_OUTPUT_PORT_TYPE
cs_out[7] <= cs_out~9.DB_MAX_OUTPUT_PORT_TYPE
cs_out[8] <= cs_out~8.DB_MAX_OUTPUT_PORT_TYPE
cs_out[9] <= cs_out~7.DB_MAX_OUTPUT_PORT_TYPE
cs_out[10] <= cs_out~6.DB_MAX_OUTPUT_PORT_TYPE
cs_out[11] <= cs_out~5.DB_MAX_OUTPUT_PORT_TYPE
cs_out[12] <= cs_out~4.DB_MAX_OUTPUT_PORT_TYPE
cs_out[13] <= cs_out~3.DB_MAX_OUTPUT_PORT_TYPE
cs_out[14] <= cs_out~2.DB_MAX_OUTPUT_PORT_TYPE
cs_out[15] <= cs_out~1.DB_MAX_OUTPUT_PORT_TYPE
a0_out <= add_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ram_cs_out <= add_reg[15].DB_MAX_OUTPUT_PORT_TYPE
data_putout[0] <= data_putout~8.DB_MAX_OUTPUT_PORT_TYPE
data_putout[1] <= data_putout~7.DB_MAX_OUTPUT_PORT_TYPE
data_putout[2] <= data_putout~6.DB_MAX_OUTPUT_PORT_TYPE
data_putout[3] <= data_putout~5.DB_MAX_OUTPUT_PORT_TYPE
data_putout[4] <= data_putout~4.DB_MAX_OUTPUT_PORT_TYPE
data_putout[5] <= data_putout~3.DB_MAX_OUTPUT_PORT_TYPE
data_putout[6] <= data_putout~2.DB_MAX_OUTPUT_PORT_TYPE
data_putout[7] <= data_putout~1.DB_MAX_OUTPUT_PORT_TYPE
write_in => write_reg~1.DATAB
read_in => read_reg~1.DATAB
ale_in => add_reg[4].CLK
ale_in => add_reg[3].CLK
ale_in => add_reg[2].CLK
ale_in => add_reg[1].CLK
ale_in => add_reg[0].CLK
ale_in => add_reg[15].CLK
clk_in => read_reg[0].CLK
clk_in => link_data_rd.CLK
clk_in => link_cs_rd.CLK
clk_in => write_reg[1].CLK
clk_in => write_reg[0].CLK
clk_in => link_data_wr.CLK
clk_in => link_cs_wr.CLK
clk_in => read_reg[1].CLK
add_in[0] => add_reg[0].DATAIN
add_in[1] => add_reg[1].DATAIN
add_in[2] => add_reg[2].DATAIN
add_in[3] => add_reg[3].DATAIN
add_in[4] => add_reg[4].DATAIN
add_in[5] => ~NO_FANOUT~
add_in[6] => ~NO_FANOUT~
add_in[7] => ~NO_FANOUT~
add_in[8] => ~NO_FANOUT~
add_in[9] => ~NO_FANOUT~
add_in[10] => ~NO_FANOUT~
add_in[11] => ~NO_FANOUT~
add_in[12] => ~NO_FANOUT~
add_in[13] => ~NO_FANOUT~
add_in[14] => ~NO_FANOUT~
add_in[15] => add_reg[15].DATAIN
rst_in => read_reg~2.OUTPUTSELECT
rst_in => read_reg~3.OUTPUTSELECT
rst_in => link_data_rd~2.OUTPUTSELECT
rst_in => link_cs_rd~2.OUTPUTSELECT
rst_in => write_reg~2.OUTPUTSELECT
rst_in => write_reg~3.OUTPUTSELECT
rst_in => link_data_wr~2.OUTPUTSELECT
rst_in => link_cs_wr~1.OUTPUTSELECT
data_in[0] => data_inout~16.DATAIN
data_in[1] => data_inout~15.DATAIN
data_in[2] => data_inout~14.DATAIN
data_in[3] => data_inout~13.DATAIN
data_in[4] => data_inout~12.DATAIN
data_in[5] => data_inout~11.DATAIN
data_in[6] => data_inout~10.DATAIN
data_in[7] => data_inout~9.DATAIN


|qep_data_bus|disp:t_disp
ledout_out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
ledout_out[7] <= <VCC>
ledsl_out[0] <= ledsl_out~4.DB_MAX_OUTPUT_PORT_TYPE
ledsl_out[1] <= ledsl_out~3.DB_MAX_OUTPUT_PORT_TYPE
ledsl_out[2] <= ledsl_out~2.DB_MAX_OUTPUT_PORT_TYPE
ledsl_out[3] <= ledsl_out~1.DB_MAX_OUTPUT_PORT_TYPE
led_out <= led_out~0.DB_MAX_OUTPUT_PORT_TYPE
clr_in => led_out~0.OUTPUTSELECT
clr_in => ledsl_out~0.IN0
clr_in => cnt_clk~0.OUTPUTSELECT
clr_in => cnt_clk~1.OUTPUTSELECT
clr_in => cnt_clk~2.OUTPUTSELECT
clr_in => cnt_clk~3.OUTPUTSELECT
clr_in => cnt_clk~4.OUTPUTSELECT
clr_in => cnt_clk~5.OUTPUTSELECT
clr_in => cnt_clk~6.OUTPUTSELECT
clr_in => cnt_clk~7.OUTPUTSELECT
clr_in => cnt_clk~8.OUTPUTSELECT
clr_in => cnt_clk~9.OUTPUTSELECT
clr_in => cnt_clk~10.OUTPUTSELECT
clr_in => cnt_clk~11.OUTPUTSELECT
clr_in => cnt_clk~12.OUTPUTSELECT
clr_in => cnt_clk~13.OUTPUTSELECT
clr_in => cnt_clk~14.OUTPUTSELECT
clr_in => cnt_clk~15.OUTPUTSELECT
clr_in => cnt_clk~16.OUTPUTSELECT
clr_in => cnt_clk~17.OUTPUTSELECT
clr_in => cnt_clk~18.OUTPUTSELECT
clr_in => cnt_clk~19.OUTPUTSELECT
clr_in => cnt_clk~20.OUTPUTSELECT
clr_in => cnt_clk~21.OUTPUTSELECT
clr_in => cnt_clk~22.OUTPUTSELECT
clr_in => cnt_clk~23.OUTPUTSELECT
clr_in => data~32.OUTPUTSELECT
clr_in => data~33.OUTPUTSELECT
clr_in => data~34.OUTPUTSELECT
clr_in => data~35.OUTPUTSELECT
clr_in => data~36.OUTPUTSELECT
clr_in => data~37.OUTPUTSELECT
clr_in => data~38.OUTPUTSELECT
clr_in => data~39.OUTPUTSELECT
clr_in => data~40.OUTPUTSELECT
clr_in => data~41.OUTPUTSELECT
clr_in => data~42.OUTPUTSELECT
clr_in => data~43.OUTPUTSELECT
clr_in => data~44.OUTPUTSELECT
clr_in => data~45.OUTPUTSELECT
clr_in => data~46.OUTPUTSELECT
clr_in => data~47.OUTPUTSELECT
clr_in => state~2.OUTPUTSELECT
clr_in => cs_reg~0.OUTPUTSELECT
clr_in => cs_reg~1.OUTPUTSELECT
clk_in => cnt_clk[22].CLK
clk_in => cnt_clk[21].CLK
clk_in => cnt_clk[20].CLK
clk_in => cnt_clk[19].CLK
clk_in => cnt_clk[18].CLK
clk_in => cnt_clk[17].CLK
clk_in => cnt_clk[16].CLK
clk_in => cnt_clk[15].CLK
clk_in => cnt_clk[14].CLK
clk_in => cnt_clk[13].CLK
clk_in => cnt_clk[12].CLK
clk_in => cnt_clk[11].CLK
clk_in => cnt_clk[10].CLK
clk_in => cnt_clk[9].CLK
clk_in => cnt_clk[8].CLK
clk_in => cnt_clk[7].CLK
clk_in => cnt_clk[6].CLK
clk_in => cnt_clk[5].CLK
clk_in => cnt_clk[4].CLK
clk_in => cnt_clk[3].CLK
clk_in => cnt_clk[2].CLK
clk_in => cnt_clk[1].CLK
clk_in => cnt_clk[0].CLK
clk_in => data[15].CLK
clk_in => data[14].CLK
clk_in => data[13].CLK
clk_in => data[12].CLK
clk_in => data[11].CLK
clk_in => data[10].CLK
clk_in => data[9].CLK
clk_in => data[8].CLK
clk_in => data[7].CLK
clk_in => data[6].CLK
clk_in => data[5].CLK
clk_in => data[4].CLK
clk_in => data[3].CLK
clk_in => data[2].CLK
clk_in => data[1].CLK
clk_in => data[0].CLK
clk_in => state.CLK
clk_in => cs_reg[1].CLK
clk_in => cs_reg[0].CLK
clk_in => cnt_clk[23].CLK
cs_in => Decoder~0.IN0
cs_in => cs_reg~1.DATAA
cs_in => ledsl_out~0.IN1
data_in[0] => data~7.DATAB
data_in[0] => data~15.DATAB
data_in[1] => data~6.DATAB
data_in[1] => data~14.DATAB
data_in[2] => data~5.DATAB
data_in[2] => data~13.DATAB
data_in[3] => data~4.DATAB
data_in[3] => data~12.DATAB
data_in[4] => data~3.DATAB
data_in[4] => data~11.DATAB
data_in[5] => data~2.DATAB
data_in[5] => data~10.DATAB
data_in[6] => data~1.DATAB
data_in[6] => data~9.DATAB
data_in[7] => data~0.DATAB
data_in[7] => data~8.DATAB
a0_in => Decoder~1.IN0


|qep_data_bus|qep4:t_qep4_0
qep_out[0] <= qep_out~7.DB_MAX_OUTPUT_PORT_TYPE
qep_out[1] <= qep_out~6.DB_MAX_OUTPUT_PORT_TYPE
qep_out[2] <= qep_out~5.DB_MAX_OUTPUT_PORT_TYPE
qep_out[3] <= qep_out~4.DB_MAX_OUTPUT_PORT_TYPE
qep_out[4] <= qep_out~3.DB_MAX_OUTPUT_PORT_TYPE
qep_out[5] <= qep_out~2.DB_MAX_OUTPUT_PORT_TYPE
qep_out[6] <= qep_out~1.DB_MAX_OUTPUT_PORT_TYPE
qep_out[7] <= qep_out~0.DB_MAX_OUTPUT_PORT_TYPE
a_in => state~0.DATAA
b_in => state~1.DATAA
clk_in => qep_reg[14].CLK
clk_in => qep_reg[13].CLK
clk_in => qep_reg[12].CLK
clk_in => qep_reg[11].CLK
clk_in => qep_reg[10].CLK
clk_in => qep_reg[9].CLK
clk_in => qep_reg[8].CLK
clk_in => qep_reg[7].CLK
clk_in => qep_reg[6].CLK
clk_in => qep_reg[5].CLK
clk_in => qep_reg[4].CLK
clk_in => qep_reg[3].CLK
clk_in => qep_reg[2].CLK
clk_in => qep_reg[1].CLK
clk_in => qep_reg[0].CLK
clk_in => prestate[1].CLK
clk_in => prestate[0].CLK
clk_in => state[1].CLK
clk_in => state[0].CLK
clk_in => a0_reg.CLK
clk_in => qep_out_reg[7].CLK
clk_in => qep_out_reg[6].CLK
clk_in => qep_out_reg[5].CLK
clk_in => qep_out_reg[4].CLK
clk_in => qep_out_reg[3].CLK
clk_in => qep_out_reg[2].CLK
clk_in => qep_out_reg[1].CLK
clk_in => qep_out_reg[0].CLK
clk_in => en_in_reg[1].CLK
clk_in => en_in_reg[0].CLK
clk_in => qep_reg[15].CLK
clr_in => qep_reg~0.OUTPUTSELECT
clr_in => qep_reg~1.OUTPUTSELECT
clr_in => qep_reg~2.OUTPUTSELECT
clr_in => qep_reg~3.OUTPUTSELECT
clr_in => qep_reg~4.OUTPUTSELECT
clr_in => qep_reg~5.OUTPUTSELECT
clr_in => qep_reg~6.OUTPUTSELECT
clr_in => qep_reg~7.OUTPUTSELECT
clr_in => qep_reg~8.OUTPUTSELECT
clr_in => qep_reg~9.OUTPUTSELECT
clr_in => qep_reg~10.OUTPUTSELECT
clr_in => qep_reg~11.OUTPUTSELECT
clr_in => qep_reg~12.OUTPUTSELECT
clr_in => qep_reg~13.OUTPUTSELECT
clr_in => qep_reg~14.OUTPUTSELECT
clr_in => qep_reg~15.OUTPUTSELECT
clr_in => prestate~0.OUTPUTSELECT
clr_in => prestate~1.OUTPUTSELECT
clr_in => state~0.OUTPUTSELECT
clr_in => state~1.OUTPUTSELECT
clr_in => a0_reg~0.OUTPUTSELECT
clr_in => qep_out_reg~16.OUTPUTSELECT
clr_in => qep_out_reg~17.OUTPUTSELECT
clr_in => qep_out_reg~18.OUTPUTSELECT
clr_in => qep_out_reg~19.OUTPUTSELECT
clr_in => qep_out_reg~20.OUTPUTSELECT
clr_in => qep_out_reg~21.OUTPUTSELECT
clr_in => qep_out_reg~22.OUTPUTSELECT
clr_in => qep_out_reg~23.OUTPUTSELECT
clr_in => en_in_reg~0.OUTPUTSELECT
clr_in => en_in_reg~1.OUTPUTSELECT
en_in => qep_out~0.OE
en_in => qep_out~1.OE
en_in => qep_out~2.OE
en_in => qep_out~3.OE
en_in => qep_out~4.OE
en_in => qep_out~5.OE
en_in => qep_out~6.OE
en_in => qep_out~7.OE
en_in => en_in_reg~1.DATAA
a0_in => a0_reg~0.DATAA


|qep_data_bus|qep4:t_qep4_1
qep_out[0] <= qep_out~7.DB_MAX_OUTPUT_PORT_TYPE
qep_out[1] <= qep_out~6.DB_MAX_OUTPUT_PORT_TYPE
qep_out[2] <= qep_out~5.DB_MAX_OUTPUT_PORT_TYPE
qep_out[3] <= qep_out~4.DB_MAX_OUTPUT_PORT_TYPE
qep_out[4] <= qep_out~3.DB_MAX_OUTPUT_PORT_TYPE
qep_out[5] <= qep_out~2.DB_MAX_OUTPUT_PORT_TYPE
qep_out[6] <= qep_out~1.DB_MAX_OUTPUT_PORT_TYPE
qep_out[7] <= qep_out~0.DB_MAX_OUTPUT_PORT_TYPE
a_in => state~0.DATAA
b_in => state~1.DATAA
clk_in => qep_reg[14].CLK
clk_in => qep_reg[13].CLK
clk_in => qep_reg[12].CLK
clk_in => qep_reg[11].CLK
clk_in => qep_reg[10].CLK
clk_in => qep_reg[9].CLK
clk_in => qep_reg[8].CLK
clk_in => qep_reg[7].CLK
clk_in => qep_reg[6].CLK
clk_in => qep_reg[5].CLK
clk_in => qep_reg[4].CLK
clk_in => qep_reg[3].CLK
clk_in => qep_reg[2].CLK
clk_in => qep_reg[1].CLK
clk_in => qep_reg[0].CLK
clk_in => prestate[1].CLK
clk_in => prestate[0].CLK
clk_in => state[1].CLK
clk_in => state[0].CLK
clk_in => a0_reg.CLK
clk_in => qep_out_reg[7].CLK
clk_in => qep_out_reg[6].CLK
clk_in => qep_out_reg[5].CLK
clk_in => qep_out_reg[4].CLK
clk_in => qep_out_reg[3].CLK
clk_in => qep_out_reg[2].CLK
clk_in => qep_out_reg[1].CLK
clk_in => qep_out_reg[0].CLK
clk_in => en_in_reg[1].CLK
clk_in => en_in_reg[0].CLK
clk_in => qep_reg[15].CLK
clr_in => qep_reg~0.OUTPUTSELECT
clr_in => qep_reg~1.OUTPUTSELECT
clr_in => qep_reg~2.OUTPUTSELECT
clr_in => qep_reg~3.OUTPUTSELECT
clr_in => qep_reg~4.OUTPUTSELECT
clr_in => qep_reg~5.OUTPUTSELECT
clr_in => qep_reg~6.OUTPUTSELECT
clr_in => qep_reg~7.OUTPUTSELECT
clr_in => qep_reg~8.OUTPUTSELECT
clr_in => qep_reg~9.OUTPUTSELECT
clr_in => qep_reg~10.OUTPUTSELECT
clr_in => qep_reg~11.OUTPUTSELECT
clr_in => qep_reg~12.OUTPUTSELECT
clr_in => qep_reg~13.OUTPUTSELECT
clr_in => qep_reg~14.OUTPUTSELECT
clr_in => qep_reg~15.OUTPUTSELECT
clr_in => prestate~0.OUTPUTSELECT
clr_in => prestate~1.OUTPUTSELECT
clr_in => state~0.OUTPUTSELECT
clr_in => state~1.OUTPUTSELECT
clr_in => a0_reg~0.OUTPUTSELECT
clr_in => qep_out_reg~16.OUTPUTSELECT