qep_data_bus.cbx.xml

来自「基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL」· XML 代码 · 共 12 行

<?xml version="1.0" ?>
<LOG_ROOT>
	<PROJECT NAME="qep_data_bus">
		<CBX_INST_ENTRY INSTANCE_NAME="|qep_data_bus|qep4:t_qep4_5|lpm_add_sub:add_rtl_18" CBX_FILE_NAME="add_sub_bfg.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|qep_data_bus|qep4:t_qep4_2|lpm_add_sub:add_rtl_15" CBX_FILE_NAME="add_sub_bfg.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|qep_data_bus|qep4:t_qep4_4|lpm_add_sub:add_rtl_17" CBX_FILE_NAME="add_sub_bfg.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|qep_data_bus|qep4:t_qep4_1|lpm_add_sub:add_rtl_14" CBX_FILE_NAME="add_sub_bfg.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|qep_data_bus|qep4:t_qep4_0|lpm_add_sub:add_rtl_13" CBX_FILE_NAME="add_sub_bfg.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|qep_data_bus|qep4:t_qep4_3|lpm_add_sub:add_rtl_16" CBX_FILE_NAME="add_sub_bfg.tdf"/>
	</PROJECT>
</LOG_ROOT>