qep_data_bus.tan.summary

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 14.300 ns
From           : clr1_in
To             : cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6]
From Clock     : 
To Clock       : clk_input
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 29.500 ns
From           : data_bus:t_data_bus|add_reg[1]
To             : data_inout[1]
From Clock     : ale_in
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 16.100 ns
From           : rst_in
To             : ledsl_out[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.300 ns
From           : addr_in[3]
To             : data_bus:t_data_bus|add_reg[3]
From Clock     : 
To Clock       : ale_in
Failed Paths   : 0

Type           : Clock Setup: 'clk_input'
Slack          : 11.100 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : 71.94 MHz ( period = 13.900 ns )
From           : qep4:t_qep4_2|prestate[0]
To             : qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15]
From Clock     : clk_input
To Clock       : clk_input
Failed Paths   : 0

Type           : Clock Hold: 'clk_input'
Slack          : 0.100 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : data_bus:t_data_bus|write_reg[1]
To             : data_bus:t_data_bus|link_cs_wr
From Clock     : clk_input
To Clock       : clk_input
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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