qep_data_bus.map.eqn

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

D1_data[3]_lut_out = (VCC) & CASCADE(A1L442);
D1_data[3] = DFFEA(D1_data[3]_lut_out, clk_input, , , A1L99, , );

--D1L61Q is disp:t_disp|data[3]~152
--operation mode is normal

D1L61Q = D1_data[3];


--D1L45 is disp:t_disp|disp_dat[3]~19
--operation mode is normal

D1L45 = G7_q[13] & (D1L35 & (D1_data[3]) # !D1L35 & D1_data[11]) # !G7_q[13] & (D1L35);

--D1L65 is disp:t_disp|disp_dat[3]~27
--operation mode is normal

D1L65 = G7_q[13] & (D1L35 & (D1_data[3]) # !D1L35 & D1_data[11]) # !G7_q[13] & (D1L35);


--D1L95 is disp:t_disp|ledout_out[0]~28
--operation mode is normal

D1L95 = D1L05 & !D1L64 & (D1L24 $ !D1L45) # !D1L05 & D1L24 & (D1L64 $ !D1L45);

--D1L06 is disp:t_disp|ledout_out[0]~35
--operation mode is normal

D1L06 = D1L05 & !D1L64 & (D1L24 $ !D1L45) # !D1L05 & D1L24 & (D1L64 $ !D1L45);


--D1L16 is disp:t_disp|ledout_out[1]~29
--operation mode is normal

D1L16 = D1L64 & (D1L24 & (D1L45) # !D1L24 & D1L05) # !D1L64 & D1L05 & (D1L24 $ D1L45);

--D1L26 is disp:t_disp|ledout_out[1]~36
--operation mode is normal

D1L26 = D1L64 & (D1L24 & (D1L45) # !D1L24 & D1L05) # !D1L64 & D1L05 & (D1L24 $ D1L45);


--D1L36 is disp:t_disp|ledout_out[2]~30
--operation mode is normal

D1L36 = D1L05 & D1L45 & (D1L64 # !D1L24) # !D1L05 & !D1L24 & D1L64 & !D1L45;

--D1L46 is disp:t_disp|ledout_out[2]~37
--operation mode is normal

D1L46 = D1L05 & D1L45 & (D1L64 # !D1L24) # !D1L05 & !D1L24 & D1L64 & !D1L45;


--D1L56 is disp:t_disp|ledout_out[3]~31
--operation mode is normal

D1L56 = D1L64 & (D1L24 & D1L05 # !D1L24 & !D1L05 & D1L45) # !D1L64 & !D1L45 & (D1L24 $ D1L05);

--D1L66 is disp:t_disp|ledout_out[3]~38
--operation mode is normal

D1L66 = D1L64 & (D1L24 & D1L05 # !D1L24 & !D1L05 & D1L45) # !D1L64 & !D1L45 & (D1L24 $ D1L05);


--D1L76 is disp:t_disp|ledout_out[4]~32
--operation mode is normal

D1L76 = D1L64 & D1L24 & (!D1L45) # !D1L64 & (D1L05 & (!D1L45) # !D1L05 & D1L24);

--D1L86 is disp:t_disp|ledout_out[4]~39
--operation mode is normal

D1L86 = D1L64 & D1L24 & (!D1L45) # !D1L64 & (D1L05 & (!D1L45) # !D1L05 & D1L24);


--D1L96 is disp:t_disp|ledout_out[5]~33
--operation mode is normal

D1L96 = D1L24 & (D1L45 $ (D1L64 # !D1L05)) # !D1L24 & D1L64 & !D1L05 & !D1L45;

--D1L07 is disp:t_disp|ledout_out[5]~40
--operation mode is normal

D1L07 = D1L24 & (D1L45 $ (D1L64 # !D1L05)) # !D1L24 & D1L64 & !D1L05 & !D1L45;


--D1L17 is disp:t_disp|ledout_out[6]~34
--operation mode is normal

D1L17 = D1L24 & (D1L45 # D1L64 $ D1L05) # !D1L24 & (D1L64 # D1L05 $ D1L45);

--D1L27 is disp:t_disp|ledout_out[6]~41
--operation mode is normal

D1L27 = D1L24 & (D1L45 # D1L64 $ D1L05) # !D1L24 & (D1L64 # D1L05 $ D1L45);


--G7_q[21] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[21]
--operation mode is clrb_cntr

G7_q[21]_lut_out = (G7_q[21] $ G7L34) & rst_in;
G7_q[21] = DFFEA(G7_q[21]_lut_out, clk_input, , , , , );

--G7L19Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[21]~3
--operation mode is clrb_cntr

G7L19Q = G7_q[21];

--G7L54 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT
--operation mode is clrb_cntr

G7L54 = CARRY(G7_q[21] & (G7L34));


--G7_q[12] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

G7_q[12]_lut_out = (G7_q[12] $ G7L52) & rst_in;
G7_q[12] = DFFEA(G7_q[12]_lut_out, clk_input, , , , , );

--G7L37Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[12]~4
--operation mode is clrb_cntr

G7L37Q = G7_q[12];

--G7L72 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

G7L72 = CARRY(G7_q[12] & (G7L52));


--C1_write_reg[1] is data_bus:t_data_bus|write_reg[1]
--operation mode is normal

C1_write_reg[1]_lut_out = C1_add_reg[15] & C1_write_reg[1] # !C1_add_reg[15] & (C1_write_reg[0]) # !rst_in;
C1_write_reg[1] = DFFEA(C1_write_reg[1]_lut_out, clk_input, , , , , );

--C1L26Q is data_bus:t_data_bus|write_reg[1]~32
--operation mode is normal

C1L26Q = C1_write_reg[1];


--C1_write_reg[0] is data_bus:t_data_bus|write_reg[0]
--operation mode is normal

C1_write_reg[0]_lut_out = C1_add_reg[15] & C1_write_reg[0] # !C1_add_reg[15] & (write_in) # !rst_in;
C1_write_reg[0] = DFFEA(C1_write_reg[0]_lut_out, clk_input, , , , , );

--C1L06Q is data_bus:t_data_bus|write_reg[0]~33
--operation mode is normal

C1L06Q = C1_write_reg[0];


--C1L54 is data_bus:t_data_bus|link_cs_wr~23
--operation mode is normal

C1L54 = rst_in & (!C1_add_reg[15]);

--C1L84 is data_bus:t_data_bus|link_cs_wr~27
--operation mode is normal

C1L84 = rst_in & (!C1_add_reg[15]);

--C1L64 is data_bus:t_data_bus|link_cs_wr~25
--operation mode is normal

C1L64 = rst_in & (!C1_add_reg[15]);


--C1_read_reg[1] is data_bus:t_data_bus|read_reg[1]
--operation mode is normal

C1_read_reg[1]_lut_out = C1_add_reg[15] & C1_read_reg[1] # !C1_add_reg[15] & (C1_read_reg[0]) # !rst_in;
C1_read_reg[1] = DFFEA(C1_read_reg[1]_lut_out, clk_input, , , , , );

--C1L75Q is data_bus:t_data_bus|read_reg[1]~37
--operation mode is normal

C1L75Q = C1_read_reg[1];


--C1_read_reg[0] is data_bus:t_data_bus|read_reg[0]
--operation mode is normal

C1_read_reg[0]_lut_out = C1_add_reg[15] & C1_read_reg[0] # !C1_add_reg[15] & (read_in) # !rst_in;
C1_read_reg[0] = DFFEA(C1_read_reg[0]_lut_out, clk_input, , , , , );

--C1L55Q is data_bus:t_data_bus|read_reg[0]~38
--operation mode is normal

C1L55Q = C1_read_reg[0];


--G7_q[20] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[20]
--operation mode is clrb_cntr

G7_q[20]_lut_out = (G7_q[20] $ G7L14) & rst_in;
G7_q[20] = DFFEA(G7_q[20]_lut_out, clk_input, , , , , );

--G7L98Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[20]~5
--operation mode is clrb_cntr

G7L98Q = G7_q[20];

--G7L34 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT
--operation mode is clrb_cntr

G7L34 = CARRY(G7_q[20] & (G7L14));


--G7_q[11] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

G7_q[11]_lut_out = (G7_q[11] $ G7L32) & rst_in;
G7_q[11] = DFFEA(G7_q[11]_lut_out, clk_input, , , , , );

--G7L17Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[11]~6
--operation mode is clrb_cntr

G7L17Q = G7_q[11];

--G7L52 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

G7L52 = CARRY(G7_q[11] & (G7L32));


--C1_link_data_wr is data_bus:t_data_bus|link_data_wr
--operation mode is normal

C1_link_data_wr_lut_out = (C1_write_reg[1] & (!C1_write_reg[0]) # !C1_write_reg[1] & C1_link_data_wr) & CASCADE(C1L64);
C1_link_data_wr = DFFEA(C1_link_data_wr_lut_out, clk_input, , , , , );

--C1L25Q is data_bus:t_data_bus|link_data_wr~54
--operation mode is normal

C1L25Q = C1_link_data_wr;


--C1_link_data_rd is data_bus:t_data_bus|link_data_rd
--operation mode is normal

C1_link_data_rd_lut_out = C1L54 & !C1_read_reg[0] & (C1_link_data_rd # !C1_read_reg[1]);
C1_link_data_rd = DFFEA(C1_link_data_rd_lut_out, clk_input, , , , , );

--C1L05Q is data_bus:t_data_bus|link_data_rd~35
--operation mode is normal

C1L05Q = C1_link_data_rd;


--C1L04 is data_bus:t_data_bus|data_putout~0
--operation mode is normal

C1L04 = C1_link_data_wr & (!C1_link_data_rd);

--C1L14 is data_bus:t_data_bus|data_putout~80
--operation mode is normal

C1L14 = C1_link_data_wr & (!C1_link_data_rd);


--D1_state is disp:t_disp|state
--operation mode is normal

D1_state_lut_out = D1_state & (rst_in & !D1L48) # !D1_state & D1L6;
D1_state = DFFEA(D1_state_lut_out, clk_input, , , , , );

--D1L58Q is disp:t_disp|state~137
--operation mode is normal

D1L58Q = D1_state;


--D1_cs_reg[1] is disp:t_disp|cs_reg[1]
--operation mode is normal

D1_cs_reg[1]_lut_out = rst_in & D1_cs_reg[0];
D1_cs_reg[1] = DFFEA(D1_cs_reg[1]_lut_out, clk_input, , , , , );

--D1L5Q is disp:t_disp|cs_reg[1]~47
--operation mode is normal

D1L5Q = D1_cs_reg[1];


--D1_cs_reg[0] is disp:t_disp|cs_reg[0]
--operation mode is normal

D1_cs_reg[0]_lut_out = rst_in & C1L1 & (C1_link_cs_wr # C1_link_cs_rd);
D1_cs_reg[0] = DFFEA(D1_cs_reg[0]_lut_out, clk_input, , , , , );

--D1L3Q is disp:t_disp|cs_reg[0]~48
--operation mode is normal

D1L3Q = D1_cs_reg[0];


--D1L48 is disp:t_disp|state~135
--operation mode is normal

D1L48 = D1_cs_reg[1] & (!D1_cs_reg[0]);

--D1L68 is disp:t_disp|state~138
--operation mode is normal

D1L68 = D1_cs_reg[1] & (!D1_cs_reg[0]);


--C1_add_reg[0] is data_bus:t_data_bus|add_reg[0]
--operation mode is normal

C1_add_reg[0]_lut_out = addr_in[0];
C1_add_reg[0] = DFFEA(C1_add_reg[0]_lut_out, !ale_in, , , , , );

--C1L92Q is data_bus:t_data_bus|add_reg[0]~11
--operation mode is normal

C1L92Q = C1_add_reg[0];


--A1L99 is rtl~33
--operation mode is normal

A1L99 = D1_state & D1L48 & !C1_add_reg[0] # !rst_in;

--A1L722 is rtl~5383
--operation mode is normal

A1L722 = D1_state & D1L48 & !C1_add_reg[0] # !rst_in;


--A1L89 is rtl~31
--operation mode is normal

A1L89 = D1_state & C1_add_reg[0] & D1L48 # !rst_in;

--A1L822 is rtl~5384
--operation mode is normal

A1L822 = D1_state & C1_add_reg[0] & D1L48 # !rst_in;


--A1L211 is rtl~4952
--operation mode is normal

A1L211 = rst_in & (C1_link_data_rd # A1L45 # !C1_link_data_wr);

--A1L922 is rtl~5385
--operation mode is normal

A1L922 = rst_in & (C1_link_data_rd # A1L45 # !C1_link_data_wr);

--A1L032 is rtl~5386
--operation mode is normal

A1L032 = rst_in & (C1_link_data_rd # A1L45 # !C1_link_data_wr);


--A1L311 is rtl~4953
--operation mode is normal

A1L311 = rst_in & (C1_link_data_rd # A1L64 # !C1_link_data_wr);

--A1L132 is rtl~5387
--operation mode is normal

A1L132 = rst_in & (C1_link_data_rd # A1L64 # !C1_link_data_wr);

--A1L232 is rtl~5388
--operation mode is normal

A1L232 = rst_in & (C1_link_data_rd # A1L64 # !C1_link_data_wr);


--A1L411 is rtl~4954
--operation mode is normal

A1L411 = rst_in & (C1_link_data_rd # A1L65 # !C1_link_data_wr);

--A1L332 is rtl~5389
--operation mode is normal

A1L332 = rst_in & (C1_link_data_rd # A1L65 # !C1_link_data_wr);

--A1L432 is rtl~5390
--operation mode is normal

A1L432 = rst_in & (C1_link_data_rd # A1L65 # !C1_link_data_wr);


--A1L511 is rtl~4955
--operation mode is normal

A1L511 = rst_in & (C1_link_data_rd # A1L84 # !C1_link_data_wr);

--A1L532 is rtl~5391
--operation mode is normal

A1L532 = rst_in & (C1_link_data_rd # A1L84 # !C1_link_data_wr);

--A1L632 is rtl~5392
--operation mode is normal

A1L632 = rst_in & (C1_link_data_rd # A1L84 # !C1_link_data_wr);


--A1L611 is rtl~4956
--operation mode is normal

A1L611 = rst_in & (C1_link_data_rd # A1L85 # !C1_link_data_wr);

--A1L732 is rtl~5393
--operation mode is normal

A1L732 = rst_in & (C1_link_data_rd # A1L85 # !C1_link_data_wr);

--A1L832 is rtl~5394
--operation mode is normal

A1L832 = rst_in & (C1_link_data_rd # A1L85 # !C1_link_data_wr);


--A1L711 is rtl~4957
--operation mode is normal

A1L711 = rst_in & (C1_link_data_rd # A1L05 # !C1_link_data_wr);

--A1L932 is rtl~5395
--operation mode is normal

A1L932 = rst_in & (C1_link_data_rd # A1L05 # !C1_link_data_wr);

--A1L042 is rtl~5396
--operation mode is normal

A1L042 = rst_in & (C1_link_data_rd # A1L05 # !C1_link_data_wr);


--A1L811 is rtl~4958
--operation mode is normal

A1L811 = rst_in & (C1_link_data_rd # A1L06 # !C1_link_data_wr);

--A1L142 is rtl~5397
--operation mode is normal

A1L142 = rst_in & (C1_link_data_rd # A1L06 # !C1_link_data_wr);

--A1L242 is rtl~5398
--operation mode is normal

A1L242 = rst_in & (C1_link_data_rd # A1L06 # !C1_link_data_wr);


--A1L911 is rtl~4959
--operation mode is normal

A1L911 = rst_in & (C1_link_data_rd # A1L25 # !C1_link_data_wr);

--A1L342 is rtl~5399
--operation mode is normal

A1L342 = rst_in & (C1_link_data_rd # A1L25 # !C1_link_data_wr);

--A1L442 is rtl~5400
--operation mode is normal

A1L442 = rst_in & (C1_link_data_rd # A1L25 # !C1_link_data_wr);


--C1L2 is data_bus:t_data_bus|Decoder~44
--operation mode is normal

C1L2 = !C1_add_reg[1] & !C1_add_reg[2] & !C1_add_reg[3] & C1_add_reg[4];