qep_data_bus.map.eqn

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_add_reg[15] is data_bus:t_data_bus|add_reg[15]
--operation mode is normal

C1_add_reg[15]_lut_out = addr_in[15];
C1_add_reg[15] = DFFEA(C1_add_reg[15]_lut_out, !ale_in, , , , , );

--C1L93Q is data_bus:t_data_bus|add_reg[15]~6
--operation mode is normal

C1L93Q = C1_add_reg[15];


--G7_q[22] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[22]
--operation mode is clrb_cntr

G7_q[22]_lut_out = (G7_q[22] $ G7L54) & rst_in;
G7_q[22] = DFFEA(G7_q[22]_lut_out, clk_input, , , , , );

--G7L39Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[22]~0
--operation mode is clrb_cntr

G7L39Q = G7_q[22];


--D1L75 is disp:t_disp|led_out~2
--operation mode is normal

D1L75 = G7_q[22] # !rst_in;

--D1L85 is disp:t_disp|led_out~3
--operation mode is normal

D1L85 = G7_q[22] # !rst_in;


--G7_q[14] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

G7_q[14]_lut_out = (G7_q[14] $ G7L92) & rst_in;
G7_q[14] = DFFEA(G7_q[14]_lut_out, clk_input, , , , , );

--G7L77Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[14]~1
--operation mode is clrb_cntr

G7L77Q = G7_q[14];

--G7L13 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

G7L13 = CARRY(G7_q[14] & (G7L92));


--G7_q[13] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

G7_q[13]_lut_out = (G7_q[13] $ G7L72) & rst_in;
G7_q[13] = DFFEA(G7_q[13]_lut_out, clk_input, , , , , );

--G7L57Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[13]~2
--operation mode is clrb_cntr

G7L57Q = G7_q[13];

--G7L92 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

G7L92 = CARRY(G7_q[13] & (G7L72));


--C1_add_reg[1] is data_bus:t_data_bus|add_reg[1]
--operation mode is normal

C1_add_reg[1]_lut_out = addr_in[1];
C1_add_reg[1] = DFFEA(C1_add_reg[1]_lut_out, !ale_in, , , , , );

--C1L13Q is data_bus:t_data_bus|add_reg[1]~7
--operation mode is normal

C1L13Q = C1_add_reg[1];


--C1_add_reg[2] is data_bus:t_data_bus|add_reg[2]
--operation mode is normal

C1_add_reg[2]_lut_out = addr_in[2];
C1_add_reg[2] = DFFEA(C1_add_reg[2]_lut_out, !ale_in, , , , , );

--C1L33Q is data_bus:t_data_bus|add_reg[2]~8
--operation mode is normal

C1L33Q = C1_add_reg[2];


--C1_add_reg[3] is data_bus:t_data_bus|add_reg[3]
--operation mode is normal

C1_add_reg[3]_lut_out = addr_in[3];
C1_add_reg[3] = DFFEA(C1_add_reg[3]_lut_out, !ale_in, , , , , );

--C1L53Q is data_bus:t_data_bus|add_reg[3]~9
--operation mode is normal

C1L53Q = C1_add_reg[3];


--C1_add_reg[4] is data_bus:t_data_bus|add_reg[4]
--operation mode is normal

C1_add_reg[4]_lut_out = addr_in[4];
C1_add_reg[4] = DFFEA(C1_add_reg[4]_lut_out, !ale_in, , , , , );

--C1L73Q is data_bus:t_data_bus|add_reg[4]~10
--operation mode is normal

C1L73Q = C1_add_reg[4];


--C1L1 is data_bus:t_data_bus|Decoder~43
--operation mode is normal

C1L1 = !C1_add_reg[1] & C1_add_reg[2] & C1_add_reg[3] & C1_add_reg[4];

--C1L41 is data_bus:t_data_bus|Decoder~56
--operation mode is normal

C1L41 = !C1_add_reg[1] & C1_add_reg[2] & C1_add_reg[3] & C1_add_reg[4];


--C1_link_cs_wr is data_bus:t_data_bus|link_cs_wr
--operation mode is normal

C1_link_cs_wr_lut_out = rst_in & C1_write_reg[1] & !C1_write_reg[0] & !C1_add_reg[15];
C1_link_cs_wr = DFFEA(C1_link_cs_wr_lut_out, clk_input, , , , , );

--C1L74Q is data_bus:t_data_bus|link_cs_wr~26
--operation mode is normal

C1L74Q = C1_link_cs_wr;


--C1_link_cs_rd is data_bus:t_data_bus|link_cs_rd
--operation mode is normal

C1_link_cs_rd_lut_out = C1L54 & (C1_read_reg[1] & (!C1_read_reg[0]) # !C1_read_reg[1] & C1_link_cs_rd);
C1_link_cs_rd = DFFEA(C1_link_cs_rd_lut_out, clk_input, , , , , );

--C1L34Q is data_bus:t_data_bus|link_cs_rd~73
--operation mode is normal

C1L34Q = C1_link_cs_rd;


--D1L18 is disp:t_disp|ledsl_out~153
--operation mode is normal

D1L18 = C1L1 & (C1_link_cs_wr # C1_link_cs_rd);

--D1L28 is disp:t_disp|ledsl_out~158
--operation mode is normal

D1L28 = C1L1 & (C1_link_cs_wr # C1_link_cs_rd);


--D1L37 is disp:t_disp|ledsl_out[0]~154
--operation mode is normal

D1L37 = G7_q[14] # G7_q[13] # D1L18 # !rst_in;

--D1L47 is disp:t_disp|ledsl_out[0]~159
--operation mode is normal

D1L47 = G7_q[14] # G7_q[13] # D1L18 # !rst_in;


--D1L57 is disp:t_disp|ledsl_out[1]~155
--operation mode is normal

D1L57 = G7_q[14] # D1L18 # !G7_q[13] # !rst_in;

--D1L67 is disp:t_disp|ledsl_out[1]~160
--operation mode is normal

D1L67 = G7_q[14] # D1L18 # !G7_q[13] # !rst_in;


--D1L77 is disp:t_disp|ledsl_out[2]~156
--operation mode is normal

D1L77 = G7_q[13] # D1L18 # !G7_q[14] # !rst_in;

--D1L87 is disp:t_disp|ledsl_out[2]~161
--operation mode is normal

D1L87 = G7_q[13] # D1L18 # !G7_q[14] # !rst_in;


--D1L97 is disp:t_disp|ledsl_out[3]~157
--operation mode is normal

D1L97 = D1L18 # !G7_q[13] # !G7_q[14] # !rst_in;

--D1L08 is disp:t_disp|ledsl_out[3]~162
--operation mode is normal

D1L08 = D1L18 # !G7_q[13] # !G7_q[14] # !rst_in;


--D1_data[4] is disp:t_disp|data[4]
--operation mode is normal

D1_data[4]_lut_out = rst_in & (A1L45 # !C1L04);
D1_data[4] = DFFEA(D1_data[4]_lut_out, clk_input, , , A1L99, , );

--D1L81Q is disp:t_disp|data[4]~137
--operation mode is normal

D1L81Q = D1_data[4];


--D1_data[8] is disp:t_disp|data[8]
--operation mode is normal

D1_data[8]_lut_out = rst_in & (A1L64 # !C1L04);
D1_data[8] = DFFEA(D1_data[8]_lut_out, clk_input, , , A1L89, , );

--D1L62Q is disp:t_disp|data[8]~138
--operation mode is normal

D1L62Q = D1_data[8];


--D1_data[12] is disp:t_disp|data[12]
--operation mode is normal

D1_data[12]_lut_out = (VCC) & CASCADE(A1L032);
D1_data[12] = DFFEA(D1_data[12]_lut_out, clk_input, , , A1L89, , );

--D1L43Q is disp:t_disp|data[12]~139
--operation mode is normal

D1L43Q = D1_data[12];


--D1L14 is disp:t_disp|disp_dat[0]~12
--operation mode is normal

D1L14 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[8] # !G7_q[13] & (D1_data[12]));

--D1L34 is disp:t_disp|disp_dat[0]~20
--operation mode is normal

D1L34 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[8] # !G7_q[13] & (D1_data[12]));


--D1_data[0] is disp:t_disp|data[0]
--operation mode is normal

D1_data[0]_lut_out = (VCC) & CASCADE(A1L232);
D1_data[0] = DFFEA(D1_data[0]_lut_out, clk_input, , , A1L99, , );

--D1L01Q is disp:t_disp|data[0]~140
--operation mode is normal

D1L01Q = D1_data[0];


--D1L24 is disp:t_disp|disp_dat[0]~13
--operation mode is normal

D1L24 = G7_q[14] & (D1L14 & (D1_data[0]) # !D1L14 & D1_data[4]) # !G7_q[14] & (D1L14);

--D1L44 is disp:t_disp|disp_dat[0]~21
--operation mode is normal

D1L44 = G7_q[14] & (D1L14 & (D1_data[0]) # !D1L14 & D1_data[4]) # !G7_q[14] & (D1L14);


--D1_data[9] is disp:t_disp|data[9]
--operation mode is normal

D1_data[9]_lut_out = rst_in & (A1L84 # !C1L04);
D1_data[9] = DFFEA(D1_data[9]_lut_out, clk_input, , , A1L89, , );

--D1L82Q is disp:t_disp|data[9]~141
--operation mode is normal

D1L82Q = D1_data[9];


--D1_data[5] is disp:t_disp|data[5]
--operation mode is normal

D1_data[5]_lut_out = rst_in & (A1L65 # !C1L04);
D1_data[5] = DFFEA(D1_data[5]_lut_out, clk_input, , , A1L99, , );

--D1L02Q is disp:t_disp|data[5]~142
--operation mode is normal

D1L02Q = D1_data[5];


--D1_data[13] is disp:t_disp|data[13]
--operation mode is normal

D1_data[13]_lut_out = (VCC) & CASCADE(A1L432);
D1_data[13] = DFFEA(D1_data[13]_lut_out, clk_input, , , A1L89, , );

--D1L63Q is disp:t_disp|data[13]~143
--operation mode is normal

D1L63Q = D1_data[13];


--D1L54 is disp:t_disp|disp_dat[1]~14
--operation mode is normal

D1L54 = G7_q[13] & (G7_q[14]) # !G7_q[13] & (G7_q[14] & D1_data[5] # !G7_q[14] & (D1_data[13]));

--D1L74 is disp:t_disp|disp_dat[1]~22
--operation mode is normal

D1L74 = G7_q[13] & (G7_q[14]) # !G7_q[13] & (G7_q[14] & D1_data[5] # !G7_q[14] & (D1_data[13]));


--D1_data[1] is disp:t_disp|data[1]
--operation mode is normal

D1_data[1]_lut_out = (VCC) & CASCADE(A1L632);
D1_data[1] = DFFEA(D1_data[1]_lut_out, clk_input, , , A1L99, , );

--D1L21Q is disp:t_disp|data[1]~144
--operation mode is normal

D1L21Q = D1_data[1];


--D1L64 is disp:t_disp|disp_dat[1]~15
--operation mode is normal

D1L64 = G7_q[13] & (D1L54 & (D1_data[1]) # !D1L54 & D1_data[9]) # !G7_q[13] & (D1L54);

--D1L84 is disp:t_disp|disp_dat[1]~23
--operation mode is normal

D1L84 = G7_q[13] & (D1L54 & (D1_data[1]) # !D1L54 & D1_data[9]) # !G7_q[13] & (D1L54);


--D1_data[6] is disp:t_disp|data[6]
--operation mode is normal

D1_data[6]_lut_out = rst_in & (A1L85 # !C1L04);
D1_data[6] = DFFEA(D1_data[6]_lut_out, clk_input, , , A1L99, , );

--D1L22Q is disp:t_disp|data[6]~145
--operation mode is normal

D1L22Q = D1_data[6];


--D1_data[10] is disp:t_disp|data[10]
--operation mode is normal

D1_data[10]_lut_out = rst_in & (A1L05 # !C1L04);
D1_data[10] = DFFEA(D1_data[10]_lut_out, clk_input, , , A1L89, , );

--D1L03Q is disp:t_disp|data[10]~146
--operation mode is normal

D1L03Q = D1_data[10];


--D1_data[14] is disp:t_disp|data[14]
--operation mode is normal

D1_data[14]_lut_out = (VCC) & CASCADE(A1L832);
D1_data[14] = DFFEA(D1_data[14]_lut_out, clk_input, , , A1L89, , );

--D1L83Q is disp:t_disp|data[14]~147
--operation mode is normal

D1L83Q = D1_data[14];


--D1L94 is disp:t_disp|disp_dat[2]~16
--operation mode is normal

D1L94 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[10] # !G7_q[13] & (D1_data[14]));

--D1L15 is disp:t_disp|disp_dat[2]~24
--operation mode is normal

D1L15 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[10] # !G7_q[13] & (D1_data[14]));


--D1_data[2] is disp:t_disp|data[2]
--operation mode is normal

D1_data[2]_lut_out = (VCC) & CASCADE(A1L042);
D1_data[2] = DFFEA(D1_data[2]_lut_out, clk_input, , , A1L99, , );

--D1L41Q is disp:t_disp|data[2]~148
--operation mode is normal

D1L41Q = D1_data[2];


--D1L05 is disp:t_disp|disp_dat[2]~17
--operation mode is normal

D1L05 = G7_q[14] & (D1L94 & (D1_data[2]) # !D1L94 & D1_data[6]) # !G7_q[14] & (D1L94);

--D1L25 is disp:t_disp|disp_dat[2]~25
--operation mode is normal

D1L25 = G7_q[14] & (D1L94 & (D1_data[2]) # !D1L94 & D1_data[6]) # !G7_q[14] & (D1L94);


--D1_data[11] is disp:t_disp|data[11]
--operation mode is normal

D1_data[11]_lut_out = rst_in & (A1L25 # !C1L04);
D1_data[11] = DFFEA(D1_data[11]_lut_out, clk_input, , , A1L89, , );

--D1L23Q is disp:t_disp|data[11]~149
--operation mode is normal

D1L23Q = D1_data[11];


--D1_data[7] is disp:t_disp|data[7]
--operation mode is normal

D1_data[7]_lut_out = rst_in & (A1L06 # !C1L04);
D1_data[7] = DFFEA(D1_data[7]_lut_out, clk_input, , , A1L99, , );

--D1L42Q is disp:t_disp|data[7]~150
--operation mode is normal

D1L42Q = D1_data[7];


--D1_data[15] is disp:t_disp|data[15]
--operation mode is normal

D1_data[15]_lut_out = (VCC) & CASCADE(A1L242);
D1_data[15] = DFFEA(D1_data[15]_lut_out, clk_input, , , A1L89, , );

--D1L04Q is disp:t_disp|data[15]~151
--operation mode is normal

D1L04Q = D1_data[15];


--D1L35 is disp:t_disp|disp_dat[3]~18
--operation mode is normal

D1L35 = G7_q[13] & (G7_q[14]) # !G7_q[13] & (G7_q[14] & D1_data[7] # !G7_q[14] & (D1_data[15]));

--D1L55 is disp:t_disp|disp_dat[3]~26
--operation mode is normal

D1L55 = G7_q[13] & (G7_q[14]) # !G7_q[13] & (G7_q[14] & D1_data[7] # !G7_q[14] & (D1_data[15]));


--D1_data[3] is disp:t_disp|data[3]
--operation mode is normal