data_bus_bak1115.v

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

module data_bus(data_inout,cs_out,a0_out,ram_cs_out,data_putout
			   ,write_in,read_in,ale_in,clk_in,addr_in,rst_in,data_in);

inout	[7:0]	data_inout;

input	write_in,read_in,ale_in,clk_in,rst_in;
input	[15:0]	addr_in;
input	[7:0]	data_in;

output	[7:0]	data_putout;
output	[15:0]	cs_out;
output	ram_cs_out;
output	a0_out;

reg		a0_reg;
reg		[15:0]	cs_reg;
reg		ram_cs_reg;
reg		[3:0]	add_reg;
	
reg		[3:0]	main_state;
//reg		[1:0]	read_reg;
//reg		[1:0]	write_reg;

//reg		[7:0]	data_in_reg;
reg		[7:0]	data_out_reg;

reg 	link_data;
reg		link_add;
reg		link_data_wr;


parameter 
		Idle		=8'b0000_0000,
		Addr_decode	=8'b0000_0001,
		Ready		=8'b0000_0010,
		Data_read	=8'b0000_0100,
		Data_write	=8'b0000_1000,
		//Stop_read	=8'b0001_0000,
		//Stop_write	=8'b0010_0000,
		//Stop_all	=8'b0100_0000,
		
		TRUE		=1'b1,
		FALSE		=1'b0;
	
assign	data_inout=(link_data)?data_in:8'bz;
assign	data_putout=(link_data_wr)?data_inout:8'bz;
assign	ram_cs_out=~addr_in[15];
assign	cs_out=(link_add)?cs_reg:16'h0000;
//assign	a0_out=(link_add)?a0_reg:1'bz;
assign	a0_out=a0_reg;


always@(posedge clk_in)
begin
	if(!rst_in)
		begin
			link_add<=FALSE;
			link_data<=FALSE;
			link_data_wr<=FALSE;
			ram_cs_reg<=1'b1;
			main_state<=Idle;
		end
	else
		begin
			case(main_state)
				Idle:
					begin
						
						link_data<=FALSE;
						link_add<=FALSE;
						ram_cs_reg<=1'b1;
						if(ale_in==1'b1)
							begin
								link_data_wr<=FALSE;
								main_state<=Addr_decode;
							end
						else
							begin
								main_state<=Idle;
							end
					end
				Addr_decode:
					begin			
						case({ale_in,addr_in[15]})
						2'b10:	begin
									ram_cs_reg<=1'b1;
									add_reg<=addr_in[4:1];
									a0_reg<=addr_in[0];	
									main_state<=Addr_decode;
								end		
						2'b11:	
								begin
									ram_cs_reg<=1'b0;
									add_reg<=add_reg;
									a0_reg<=addr_in[0];
									main_state<=Addr_decode;
								end
						2'b01:
								begin
									ram_cs_reg<=ram_cs_reg;
									add_reg<=add_reg;
									a0_reg<=a0_reg;
									main_state<=Ready;
								end
						2'b00:
								begin
									ram_cs_reg<=ram_cs_reg;
									add_reg<=add_reg;
									a0_reg<=a0_reg;
									main_state<=Ready;
								end		
						default:
								main_state<=main_state;
						endcase
						
					end
				Ready:
					begin
						case({write_in,read_in})
							2'b01:	
								begin									
									link_add<=FALSE;
									if(ram_cs_reg==1'b1)
										link_data_wr<=TRUE;
									else
										link_data_wr<=FALSE;
									main_state<=Data_write;
									
								end
							2'b10:
								begin
									
									link_data_wr<=FALSE;
									if(ram_cs_reg==1'b1)
										link_add<=TRUE;
									else
										link_add<=FALSE;
									main_state<=Data_read;
									
								end
							default:
								begin
									link_data_wr<=link_data_wr;
									main_state<=main_state;
									link_add<=link_add;
								end
						endcase
					end
				Data_read:
					begin
						case({read_in,ram_cs_reg})
							2'b01:
									begin
										link_data<=TRUE;
										main_state<=Data_read;
									end
							2'b11:
									begin
										link_data<=FALSE;
										main_state<=Idle;
									end
							2'b00:
									begin
										link_data<=FALSE;
										main_state<=Data_read;
									end
							2'b10:
									begin
										link_data<=FALSE;
										main_state<=Idle;
									end
							default:
									begin
										link_data<=link_data;
										main_state<=main_state;
									end
							endcase
				
						end								
				Data_write:
						begin
							case({write_in,ram_cs_reg})
								2'b01:
									begin
										link_add<=TRUE;
										main_state<=Data_write;
									end
								2'b11:
									begin
										link_add<=FALSE;
										main_state<=Idle;	
									end
								2'b00:
									begin
										link_add<=FALSE;
										main_state<=Data_write;
									end
								2'b10:
									begin
										link_add<=FALSE;
										main_state<=Idle;	
									end
								default:
									begin
										link_add<=link_add;
										main_state<=main_state;
									end
							endcase
						end
				default:
						main_state<=Idle;
			endcase
		end
end

always @(add_reg)
begin
	case(add_reg)
		4'b0000:cs_reg<=16'b0000_0000_0000_0001;
		4'b0001:cs_reg<=16'b0000_0000_0000_0010;
		4'b0010:cs_reg<=16'b0000_0000_0000_0100;
		4'b0011:cs_reg<=16'b0000_0000_0000_1000;
		
		4'b0100:cs_reg<=16'b0000_0000_0001_0000;
		4'b0101:cs_reg<=16'b0000_0000_0010_0000;
		4'b0110:cs_reg<=16'b0000_0000_0100_0000;
		4'b0111:cs_reg<=16'b0000_0000_1000_0000;
		
		4'b1000:cs_reg<=16'b0000_0001_0000_0000;
		4'b1001:cs_reg<=16'b0000_0010_0000_0000;
		4'b1010:cs_reg<=16'b0000_0100_0000_0000;
		4'b1011:cs_reg<=16'b0000_1000_0000_0000;
		
		4'b1100:cs_reg<=16'b0001_0000_0000_0000;
		4'b1101:cs_reg<=16'b0010_0000_0000_0000;
		4'b1110:cs_reg<=16'b0100_0000_0000_0000;
		4'b1111:cs_reg<=16'b1000_0000_0000_0000;
	default:	cs_reg<=16'h0000;
	endcase
end
endmodule