qep_data_bus.tcl

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

if { ![project_exists {qep_data_bus}] } {
    project_new {qep_data_bus}
} else {
    project_open {qep_data_bus}
}
set_project_settings -cmp {qep_data_bus}
if { ![project_settings_exist -sim qep_data_bus] } {
        set_project_settings -sim qep_data_bus
}
set_global_assignment -section_id {qep_data_bus} -name {EDA_DESIGN_ENTRY_SYNTHESIS_TOOL} {LEONARDOSPECTRUM}
set_global_assignment -section_id {qep_data_bus} -name {EDA_SIMULATION_TOOL} {MODELSIM (VERILOG HDL OUTPUT FROM QUARTUS II)}
set_global_assignment -name {EDIF_FILE} {qep_data_bus.edf}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_USE_LMF} {mentor.lmf}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_INPUT_GND_NAME} {GND}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_INPUT_VCC_NAME} {VCC}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_SHOW_LMF_MAPPING_MESSAGES} {OFF}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_RUN_TOOL_AUTOMATICALLY} {OFF}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_INPUT_DATA_FORMAT} {EDIF}
set_global_assignment -section_id {eda_design_synthesis} -name {EDA_OUTPUT_DATA_FORMAT} {EDIF}
set_global_assignment -section_id {eda_simulation} -name {EDA_FLATTEN_BUSES} {OFF}
set_global_assignment -section_id {eda_timing_analysis} -name {EDA_FLATTEN_BUSES} {OFF}
set_global_assignment -section_id {qep_data_bus} -name {DEVICE} {EPF10K30ATC144-1}
set_global_assignment -name {FAMILY} {FLEX10KA}
set_global_assignment -name {PROJECT_SHOW_ENTITY_NAME} {OFF}
project close