qep_data_bus.map.rpt

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

Analysis & Synthesis report for qep_data_bus
Thu Dec 15 21:16:20 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Parameter Settings for User Entity Instance: data_bus:t_data_bus
  9. Parameter Settings for User Entity Instance: disp:t_disp
 10. Parameter Settings for Inferred Entity Instance: disp:t_disp|lpm_counter:cnt_clk_rtl_0
 11. Parameter Settings for Inferred Entity Instance: cnt_pulse:t_cnt_pulse_5|lpm_counter:cnt_reg_rtl_1
 12. Parameter Settings for Inferred Entity Instance: cnt_pulse:t_cnt_pulse_4|lpm_counter:cnt_reg_rtl_2
 13. Parameter Settings for Inferred Entity Instance: cnt_pulse:t_cnt_pulse_3|lpm_counter:cnt_reg_rtl_3
 14. Parameter Settings for Inferred Entity Instance: cnt_pulse:t_cnt_pulse_2|lpm_counter:cnt_reg_rtl_4
 15. Parameter Settings for Inferred Entity Instance: cnt_pulse:t_cnt_pulse_1|lpm_counter:cnt_reg_rtl_5
 16. Parameter Settings for Inferred Entity Instance: cnt_pulse:t_cnt_pulse_0|lpm_counter:cnt_reg_rtl_6
 17. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7
 18. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_1|lpm_counter:qep_reg_rtl_8
 19. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9
 20. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_3|lpm_counter:qep_reg_rtl_10
 21. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_4|lpm_counter:qep_reg_rtl_11
 22. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_5|lpm_counter:qep_reg_rtl_12
 23. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_0|lpm_add_sub:add_rtl_13
 24. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_1|lpm_add_sub:add_rtl_14
 25. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_2|lpm_add_sub:add_rtl_15
 26. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_3|lpm_add_sub:add_rtl_16
 27. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_4|lpm_add_sub:add_rtl_17
 28. Parameter Settings for Inferred Entity Instance: qep4:t_qep4_5|lpm_add_sub:add_rtl_18
 29. Analysis & Synthesis Equations
 30. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 15 21:16:20 2005         ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name               ; qep_data_bus                                  ;
; Top-level Entity Name       ; qep_data_bus                                  ;
; Family                      ; FLEX10KA                                      ;
; Total logic elements        ; 903                                           ;
; Total pins                  ; 70                                            ;
; Total memory bits           ; 0                                             ;
+-----------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                 ;
+------------------------------------------------------------+------------------+---------------+
; Option                                                     ; Setting          ; Default Value ;
+------------------------------------------------------------+------------------+---------------+
; Device                                                     ; EPF10K30ATC144-1 ;               ;
; Top-level entity name                                      ; qep_data_bus     ; qep_data_bus  ;
; Family name                                                ; FLEX10KA         ; Stratix       ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K       ; Speed            ; Area          ;
; Type of Retiming Performed During Resynthesis              ; Full             ;               ;
; Resynthesis Optimization Effort                            ; Normal           ;               ;
; Physical Synthesis Level for Resynthesis                   ; Normal           ;               ;
; Use Generated Physical Constraints File                    ; On               ;               ;
; Use smart compilation                                      ; Off              ; Off           ;
; Create Debugging Nodes for IP Cores                        ; off              ; off           ;
; Preserve fewer node names                                  ; On               ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off              ; Off           ;
; Verilog Version                                            ; Verilog_2001     ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93           ; VHDL93        ;
; State Machine Processing                                   ; Auto             ; Auto          ;
; Extract Verilog State Machines                             ; On               ; On            ;
; Extract VHDL State Machines                                ; On               ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On               ; On            ;
; NOT Gate Push-Back                                         ; On               ; On            ;
; Power-Up Don't Care                                        ; On               ; On            ;
; Remove Redundant Logic Cells                               ; Off              ; Off           ;
; Remove Duplicate Registers                                 ; On               ; On            ;
; Ignore CARRY Buffers                                       ; Off              ; Off           ;
; Ignore CASCADE Buffers                                     ; Off              ; Off           ;
; Ignore GLOBAL Buffers                                      ; Off              ; Off           ;
; Ignore ROW GLOBAL Buffers                                  ; Off              ; Off           ;
; Ignore LCELL Buffers                                       ; Off              ; Off           ;
; Ignore SOFT Buffers                                        ; On               ; On            ;
; Limit AHDL Integers to 32 Bits                             ; Off              ; Off           ;
; Auto Implement in ROM                                      ; Off              ; Off           ;
; Carry Chain Length -- FLEX 10K                             ; 32               ; 32            ;
; Cascade Chain Length                                       ; 2                ; 2             ;
; Auto Carry Chains                                          ; On               ; On            ;
; Auto Open-Drain Pins                                       ; On               ; On            ;
; Remove Duplicate Logic                                     ; On               ; On            ;
; Auto ROM Replacement                                       ; On               ; On            ;
; Auto RAM Replacement                                       ; On               ; On            ;
; Auto Clock Enable Replacement                              ; On               ; On            ;
; Auto Resource Sharing                                      ; Off              ; Off           ;
; Allow Any RAM Size For Recognition                         ; Off              ; Off           ;
; Allow Any ROM Size For Recognition                         ; Off              ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives ; Off              ; Off           ;