cnt_pulse.v

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

module cnt_pulse(cnt_out,fin_in,din_in,clk_in,en_in,clr_in,a0_in);
input	fin_in,din_in,clk_in,en_in,clr_in,a0_in;
output	[7:0]	cnt_out;
reg		[15:0]	cnt_reg;
reg		[7:0]	cnt_out_reg;
reg		cnt_state,cnt_prestate,din_reg;
reg		a0_reg;
reg		[1:0]	en_in_reg;

assign	cnt_out=(en_in)?cnt_out_reg:8'bz;

always@(posedge clk_in)
begin
	if(!clr_in)
		begin 
			cnt_state<=1'b0;
			cnt_prestate<=1'b0;
			cnt_reg<=15'b0;
			din_reg<=1'b0;
		end
	else
		begin
			cnt_state<=fin_in;
			cnt_prestate<=cnt_state;
			din_reg<=din_in;
			
			if({cnt_prestate,cnt_state}==2'b01)
				if(din_reg==1'b1)
					cnt_reg<=cnt_reg+16'b1;
				else
					cnt_reg<=cnt_reg-16'b1;
			else
				cnt_reg<=cnt_reg;	
					
		end
end

always@(posedge clk_in)
begin
	if(!clr_in)
		begin 
			a0_reg<=1'b0;
			cnt_out_reg<=8'b0;
			en_in_reg<=2'b00;
		end
	else
		begin
			a0_reg<=a0_in;
			en_in_reg[1]<=en_in_reg[0];
			en_in_reg[0]<=en_in;
			if(en_in_reg==2'b01)
			begin
				case(a0_reg)
					1'b0:cnt_out_reg<=cnt_reg[7:0];
					1'b1:cnt_out_reg<=cnt_reg[15:8];
					default:cnt_out_reg<=8'bz;
				endcase	
			end
			else
				cnt_out_reg<=cnt_out_reg;							
		end
end
endmodule