qep_data_bus.edf

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

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  (cell data_bus_notri (cellType GENERIC)
   (view INTERFACE_unfold_2093  (viewType NETLIST)
    (interface 
     (port (array (rename data_inout "data_inout[7:0]") 8 )(direction INPUT))
     (port (array (rename cs_out_1 "cs_out_1[5:0]") 6 )(direction OUTPUT))
     (port (array (rename cs_out "cs_out[14:8]") 7 )(direction OUTPUT))
     (port (array (rename data_putout "data_putout[7:0]") 8 )(direction OUTPUT))
     (port link_data (direction OUTPUT))
     (port link_add (direction OUTPUT))
     (port data_out_reg_0 (direction OUTPUT))
     (port (array (rename data_in "data_in[7:0]") 8 )(direction INPUT))
     (port data_out_reg_1 (direction OUTPUT))
     (port data_out_reg_2 (direction OUTPUT))
     (port data_out_reg_3 (direction OUTPUT))
     (port data_out_reg_4 (direction OUTPUT))
     (port data_out_reg_5 (direction OUTPUT))
     (port data_out_reg_6 (direction OUTPUT))
     (port data_out_reg_7 (direction OUTPUT))
     (port (array (rename addr_in_1 "addr_in_1[4:0]") 5 )(direction INPUT))
     (port a0_reg (direction OUTPUT))
     (port clk_in (direction INPUT))
     (port (array (rename ale_in_modgen_select_14 "ale_in_modgen_select_14[2:2]") 1 )(direction INPUT))
     (port (array (rename read_in_modgen_select_10 "read_in_modgen_select_10[2:1]") 2 )(direction INPUT))
     (port ram_cs_out (direction OUTPUT))
     (port (array (rename addr_in "addr_in[15:15]") 1 )(direction INPUT))
     (port rst_in (direction INPUT)))
    (property attx45 (string ""))
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    (property attx48 (string ""))
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    (property attx62 (string ""))
    (property attx63 (string ""))
    (property attx64 (string ""))
    (property attx65 (string ""))
    (contents 
     (instance reg_a0_reg (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_add_reg_3 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_add_reg_2 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_add_reg_1 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_add_reg_0 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_7 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_6 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_5 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_4 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_3 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_2 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_1 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_out_reg_0 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_link_add (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_link_data (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_link_data_wr (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_ram_cs_reg (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_main_state_5 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_main_state_4 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_main_state_3 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_main_state_2 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_main_state_1 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_main_state_0 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_read_reg_1 (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_read_reg_0 (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_write_reg_1 (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_write_reg_0 (viewRef NETLIST  (cellRef DFFE (libraryRef flex10a ))))
     (instance reg_data_in_reg_7 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_6 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_5 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_4 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_3 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_2 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_1 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance reg_data_in_reg_0 (viewRef NETLIST  (cellRef DFF (libraryRef flex10a ))))
     (instance ix62 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN2')+(IN1' IN3 IN4))")))
     (instance ix63 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1 IN2))")))
     (instance ix64 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1')+(IN2')+(IN3))")))
     (instance ix65 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1 IN2))")))
     (instance ix66 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1 IN2))")))
     (instance ix67 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1')+(IN2')+(IN3))")))
     (instance ix68 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1 IN2))")))
     (instance ix69 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1 IN2))")))
     (instance ix70 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (property lut_function (string "((IN1 IN2))")))
     (instance ix71 (viewRef NETLIST  (cellRef LUT (libraryRef flex10a )))
      (pr