qep_data_bus.fit.eqn

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

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--C1_add_reg[15] is data_bus:t_data_bus|add_reg[15] at LC3_F36
--operation mode is normal

C1_add_reg[15]_lut_out = addr_in[15];
C1_add_reg[15] = DFFEA(C1_add_reg[15]_lut_out, !ale_in, , , , , );

--C1L93Q is data_bus:t_data_bus|add_reg[15]~6 at LC3_F36
--operation mode is normal

C1L93Q = C1_add_reg[15];


--G7_q[22] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[22] at LC8_F34
--operation mode is clrb_cntr

G7_q[22]_lut_out = (G7_q[22] $ G7L54) & rst_in;
G7_q[22] = DFFEA(G7_q[22]_lut_out, GLOBAL(clk_input), , , , , );

--G7L39Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[22]~0 at LC8_F34
--operation mode is clrb_cntr

G7L39Q = G7_q[22];


--D1L75 is disp:t_disp|led_out~2 at LC1_F28
--operation mode is normal

D1L75 = G7_q[22] # !rst_in;

--D1L85 is disp:t_disp|led_out~3 at LC1_F28
--operation mode is normal

D1L85 = G7_q[22] # !rst_in;


--G7_q[14] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[14] at LC8_F32
--operation mode is clrb_cntr

G7_q[14]_lut_out = (G7_q[14] $ G7L92) & rst_in;
G7_q[14] = DFFEA(G7_q[14]_lut_out, GLOBAL(clk_input), , , , , );

--G7L77Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[14]~1 at LC8_F32
--operation mode is clrb_cntr

G7L77Q = G7_q[14];

--G7L13 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT at LC8_F32
--operation mode is clrb_cntr

G7L13 = CARRY(G7_q[14] & (G7L92));


--G7_q[13] is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[13] at LC7_F32
--operation mode is clrb_cntr

G7_q[13]_lut_out = (G7_q[13] $ G7L72) & rst_in;
G7_q[13] = DFFEA(G7_q[13]_lut_out, GLOBAL(clk_input), , , , , );

--G7L57Q is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|q[13]~2 at LC7_F32
--operation mode is clrb_cntr

G7L57Q = G7_q[13];

--G7L92 is disp:t_disp|lpm_counter:cnt_clk_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT at LC7_F32
--operation mode is clrb_cntr

G7L92 = CARRY(G7_q[13] & (G7L72));


--C1_add_reg[1] is data_bus:t_data_bus|add_reg[1] at LC5_F36
--operation mode is normal

C1_add_reg[1]_lut_out = addr_in[1];
C1_add_reg[1] = DFFEA(C1_add_reg[1]_lut_out, !ale_in, , , , , );

--C1L13Q is data_bus:t_data_bus|add_reg[1]~7 at LC5_F36
--operation mode is normal

C1L13Q = C1_add_reg[1];


--C1_add_reg[2] is data_bus:t_data_bus|add_reg[2] at LC1_F36
--operation mode is normal

C1_add_reg[2]_lut_out = addr_in[2];
C1_add_reg[2] = DFFEA(C1_add_reg[2]_lut_out, !ale_in, , , , , );

--C1L33Q is data_bus:t_data_bus|add_reg[2]~8 at LC1_F36
--operation mode is normal

C1L33Q = C1_add_reg[2];


--C1_add_reg[3] is data_bus:t_data_bus|add_reg[3] at LC2_F31
--operation mode is normal

C1_add_reg[3]_lut_out = addr_in[3];
C1_add_reg[3] = DFFEA(C1_add_reg[3]_lut_out, !ale_in, , , , , );

--C1L53Q is data_bus:t_data_bus|add_reg[3]~9 at LC2_F31
--operation mode is normal

C1L53Q = C1_add_reg[3];


--C1_add_reg[4] is data_bus:t_data_bus|add_reg[4] at LC2_F21
--operation mode is normal

C1_add_reg[4]_lut_out = addr_in[4];
C1_add_reg[4] = DFFEA(C1_add_reg[4]_lut_out, !ale_in, , , , , );

--C1L73Q is data_bus:t_data_bus|add_reg[4]~10 at LC2_F21
--operation mode is normal

C1L73Q = C1_add_reg[4];


--C1L1 is data_bus:t_data_bus|Decoder~43 at LC5_F29
--operation mode is normal

C1L1 = !C1_add_reg[1] & C1_add_reg[2] & C1_add_reg[3] & C1_add_reg[4];

--C1L41 is data_bus:t_data_bus|Decoder~56 at LC5_F29
--operation mode is normal

C1L41 = !C1_add_reg[1] & C1_add_reg[2] & C1_add_reg[3] & C1_add_reg[4];


--C1_link_cs_wr is data_bus:t_data_bus|link_cs_wr at LC5_F33
--operation mode is normal

C1_link_cs_wr_lut_out = rst_in & C1_write_reg[1] & !C1_write_reg[0] & !C1_add_reg[15];
C1_link_cs_wr = DFFEA(C1_link_cs_wr_lut_out, GLOBAL(clk_input), , , , , );

--C1L74Q is data_bus:t_data_bus|link_cs_wr~26 at LC5_F33
--operation mode is normal

C1L74Q = C1_link_cs_wr;


--C1_link_cs_rd is data_bus:t_data_bus|link_cs_rd at LC8_F33
--operation mode is normal

C1_link_cs_rd_lut_out = C1L54 & (C1_read_reg[1] & (!C1_read_reg[0]) # !C1_read_reg[1] & C1_link_cs_rd);
C1_link_cs_rd = DFFEA(C1_link_cs_rd_lut_out, GLOBAL(clk_input), , , , , );

--C1L34Q is data_bus:t_data_bus|link_cs_rd~73 at LC8_F33
--operation mode is normal

C1L34Q = C1_link_cs_rd;


--D1L18 is disp:t_disp|ledsl_out~153 at LC7_F29
--operation mode is normal

D1L18 = C1L1 & (C1_link_cs_wr # C1_link_cs_rd);

--D1L28 is disp:t_disp|ledsl_out~158 at LC7_F29
--operation mode is normal

D1L28 = C1L1 & (C1_link_cs_wr # C1_link_cs_rd);


--D1L37 is disp:t_disp|ledsl_out[0]~154 at LC3_F1
--operation mode is normal

D1L37 = G7_q[14] # G7_q[13] # D1L18 # !rst_in;

--D1L47 is disp:t_disp|ledsl_out[0]~159 at LC3_F1
--operation mode is normal

D1L47 = G7_q[14] # G7_q[13] # D1L18 # !rst_in;


--D1L57 is disp:t_disp|ledsl_out[1]~155 at LC5_F4
--operation mode is normal

D1L57 = G7_q[14] # D1L18 # !G7_q[13] # !rst_in;

--D1L67 is disp:t_disp|ledsl_out[1]~160 at LC5_F4
--operation mode is normal

D1L67 = G7_q[14] # D1L18 # !G7_q[13] # !rst_in;


--D1L77 is disp:t_disp|ledsl_out[2]~156 at LC4_F6
--operation mode is normal

D1L77 = G7_q[13] # D1L18 # !G7_q[14] # !rst_in;

--D1L87 is disp:t_disp|ledsl_out[2]~161 at LC4_F6
--operation mode is normal

D1L87 = G7_q[13] # D1L18 # !G7_q[14] # !rst_in;


--D1L97 is disp:t_disp|ledsl_out[3]~157 at LC4_F5
--operation mode is normal

D1L97 = D1L18 # !G7_q[13] # !G7_q[14] # !rst_in;

--D1L08 is disp:t_disp|ledsl_out[3]~162 at LC4_F5
--operation mode is normal

D1L08 = D1L18 # !G7_q[13] # !G7_q[14] # !rst_in;


--D1_data[4] is disp:t_disp|data[4] at LC1_F14
--operation mode is normal

D1_data[4]_lut_out = rst_in & (A1L55 # !C1L04);
D1_data[4] = DFFEA(D1_data[4]_lut_out, GLOBAL(clk_input), , , A1L001, , );

--D1L81Q is disp:t_disp|data[4]~137 at LC1_F14
--operation mode is normal

D1L81Q = D1_data[4];


--D1_data[8] is disp:t_disp|data[8] at LC8_F18
--operation mode is normal

D1_data[8]_lut_out = rst_in & (A1L74 # !C1L04);
D1_data[8] = DFFEA(D1_data[8]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L62Q is disp:t_disp|data[8]~138 at LC8_F18
--operation mode is normal

D1L62Q = D1_data[8];


--D1_data[12] is disp:t_disp|data[12] at LC2_F4
--operation mode is normal

D1_data[12]_lut_out = (VCC) & CASCADE(A1L132);
D1_data[12] = DFFEA(D1_data[12]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L43Q is disp:t_disp|data[12]~139 at LC2_F4
--operation mode is normal

D1L43Q = D1_data[12];


--D1L14 is disp:t_disp|disp_dat[0]~12 at LC7_F1
--operation mode is normal

D1L14 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[8] # !G7_q[13] & (D1_data[12]));

--D1L34 is disp:t_disp|disp_dat[0]~20 at LC7_F1
--operation mode is normal

D1L34 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[8] # !G7_q[13] & (D1_data[12]));


--D1_data[0] is disp:t_disp|data[0] at LC2_F18
--operation mode is normal

D1_data[0]_lut_out = (VCC) & CASCADE(A1L332);
D1_data[0] = DFFEA(D1_data[0]_lut_out, GLOBAL(clk_input), , , A1L001, , );

--D1L01Q is disp:t_disp|data[0]~140 at LC2_F18
--operation mode is normal

D1L01Q = D1_data[0];


--D1L24 is disp:t_disp|disp_dat[0]~13 at LC5_F1
--operation mode is normal

D1L24 = G7_q[14] & (D1L14 & (D1_data[0]) # !D1L14 & D1_data[4]) # !G7_q[14] & (D1L14);

--D1L44 is disp:t_disp|disp_dat[0]~21 at LC5_F1
--operation mode is normal

D1L44 = G7_q[14] & (D1L14 & (D1_data[0]) # !D1L14 & D1_data[4]) # !G7_q[14] & (D1L14);


--D1_data[9] is disp:t_disp|data[9] at LC6_F22
--operation mode is normal

D1_data[9]_lut_out = rst_in & (A1L94 # !C1L04);
D1_data[9] = DFFEA(D1_data[9]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L82Q is disp:t_disp|data[9]~141 at LC6_F22
--operation mode is normal

D1L82Q = D1_data[9];


--D1_data[5] is disp:t_disp|data[5] at LC7_F22
--operation mode is normal

D1_data[5]_lut_out = rst_in & (A1L75 # !C1L04);
D1_data[5] = DFFEA(D1_data[5]_lut_out, GLOBAL(clk_input), , , A1L001, , );

--D1L02Q is disp:t_disp|data[5]~142 at LC7_F22
--operation mode is normal

D1L02Q = D1_data[5];


--D1_data[13] is disp:t_disp|data[13] at LC4_F22
--operation mode is normal

D1_data[13]_lut_out = (VCC) & CASCADE(A1L532);
D1_data[13] = DFFEA(D1_data[13]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L63Q is disp:t_disp|data[13]~143 at LC4_F22
--operation mode is normal

D1L63Q = D1_data[13];


--D1L54 is disp:t_disp|disp_dat[1]~14 at LC8_F22
--operation mode is normal

D1L54 = G7_q[13] & (G7_q[14]) # !G7_q[13] & (G7_q[14] & D1_data[5] # !G7_q[14] & (D1_data[13]));

--D1L74 is disp:t_disp|disp_dat[1]~22 at LC8_F22
--operation mode is normal

D1L74 = G7_q[13] & (G7_q[14]) # !G7_q[13] & (G7_q[14] & D1_data[5] # !G7_q[14] & (D1_data[13]));


--D1_data[1] is disp:t_disp|data[1] at LC2_F22
--operation mode is normal

D1_data[1]_lut_out = (VCC) & CASCADE(A1L732);
D1_data[1] = DFFEA(D1_data[1]_lut_out, GLOBAL(clk_input), , , A1L001, , );

--D1L21Q is disp:t_disp|data[1]~144 at LC2_F22
--operation mode is normal

D1L21Q = D1_data[1];


--D1L64 is disp:t_disp|disp_dat[1]~15 at LC5_F22
--operation mode is normal

D1L64 = G7_q[13] & (D1L54 & (D1_data[1]) # !D1L54 & D1_data[9]) # !G7_q[13] & (D1L54);

--D1L84 is disp:t_disp|disp_dat[1]~23 at LC5_F22
--operation mode is normal

D1L84 = G7_q[13] & (D1L54 & (D1_data[1]) # !D1L54 & D1_data[9]) # !G7_q[13] & (D1L54);


--D1_data[6] is disp:t_disp|data[6] at LC4_F24
--operation mode is normal

D1_data[6]_lut_out = rst_in & (A1L95 # !C1L04);
D1_data[6] = DFFEA(D1_data[6]_lut_out, GLOBAL(clk_input), , , A1L001, , );

--D1L22Q is disp:t_disp|data[6]~145 at LC4_F24
--operation mode is normal

D1L22Q = D1_data[6];


--D1_data[10] is disp:t_disp|data[10] at LC5_F24
--operation mode is normal

D1_data[10]_lut_out = rst_in & (A1L15 # !C1L04);
D1_data[10] = DFFEA(D1_data[10]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L03Q is disp:t_disp|data[10]~146 at LC5_F24
--operation mode is normal

D1L03Q = D1_data[10];


--D1_data[14] is disp:t_disp|data[14] at LC8_F24
--operation mode is normal

D1_data[14]_lut_out = (VCC) & CASCADE(A1L932);
D1_data[14] = DFFEA(D1_data[14]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L83Q is disp:t_disp|data[14]~147 at LC8_F24
--operation mode is normal

D1L83Q = D1_data[14];


--D1L94 is disp:t_disp|disp_dat[2]~16 at LC6_F24
--operation mode is normal

D1L94 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[10] # !G7_q[13] & (D1_data[14]));

--D1L15 is disp:t_disp|disp_dat[2]~24 at LC6_F24
--operation mode is normal

D1L15 = G7_q[14] & (G7_q[13]) # !G7_q[14] & (G7_q[13] & D1_data[10] # !G7_q[13] & (D1_data[14]));


--D1_data[2] is disp:t_disp|data[2] at LC3_F24
--operation mode is normal

D1_data[2]_lut_out = (VCC) & CASCADE(A1L142);
D1_data[2] = DFFEA(D1_data[2]_lut_out, GLOBAL(clk_input), , , A1L001, , );

--D1L41Q is disp:t_disp|data[2]~148 at LC3_F24
--operation mode is normal

D1L41Q = D1_data[2];


--D1L05 is disp:t_disp|disp_dat[2]~17 at LC1_F24
--operation mode is normal

D1L05 = G7_q[14] & (D1L94 & (D1_data[2]) # !D1L94 & D1_data[6]) # !G7_q[14] & (D1L94);

--D1L25 is disp:t_disp|disp_dat[2]~25 at LC1_F24
--operation mode is normal

D1L25 = G7_q[14] & (D1L94 & (D1_data[2]) # !D1L94 & D1_data[6]) # !G7_q[14] & (D1L94);


--D1_data[11] is disp:t_disp|data[11] at LC5_F18
--operation mode is normal

D1_data[11]_lut_out = rst_in & (A1L35 # !C1L04);
D1_data[11] = DFFEA(D1_data[11]_lut_out, GLOBAL(clk_input), , , A1L99, , );

--D1L23Q is disp:t_disp|data[11]~149 at LC5_F18
--operation mode is normal

D1L23Q = D1_data[11];


--D1_data[7] is disp:t_disp|data[7] at LC7_F4
--operation mode is normal

D1_data[7]_lut_out = rst_in & (A1L16 # !C1L04);