qep_data_bus.flow.rpt

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

Flow report for qep_data_bus
Thu Dec 15 21:17:02 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------+-----------------------------------------------+
; Flow Status             ; Successful - Thu Dec 15 21:17:02 2005         ;
; Quartus II Version      ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name           ; qep_data_bus                                  ;
; Top-level Entity Name   ; qep_data_bus                                  ;
; Family                  ; FLEX10KA                                      ;
; Device                  ; EPF10K30ATC144-1                              ;
; Timing Models           ; Final                                         ;
; Met timing requirements ; Yes                                           ;
; Total logic elements    ; 904 / 1,728 ( 52 % )                          ;
; Total pins              ; 70 / 102 ( 68 % )                             ;
; Total memory bits       ; 0 / 12,288 ( 0 % )                            ;
+-------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/15/2005 21:16:07 ;
; Main task         ; Compilation         ;
; Revision Name     ; qep_data_bus        ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:13     ;
; Fitter               ; 00:00:34     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:03     ;
; Total                ; 00:00:52     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off qep_data_bus -c qep_data_bus
quartus_fit --read_settings_files=off --write_settings_files=off qep_data_bus -c qep_data_bus
quartus_asm --read_settings_files=off --write_settings_files=off qep_data_bus -c qep_data_bus
quartus_tan --read_settings_files=off --write_settings_files=off qep_data_bus -c qep_data_bus