data_bus.v

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

module data_bus(data_inout,cs_out,a0_out,ram_cs_out,data_putout
			   ,write_in,read_in,ale_in,clk_in,add_in,rst_in,data_in);

inout	[7:0]	data_inout;

input	write_in,read_in,ale_in,clk_in,rst_in;
input	[15:0]	add_in;
input	[7:0]	data_in;

output	[7:0]	data_putout;
output	[15:0]	cs_out;
output	ram_cs_out;
output	a0_out;

reg		[15:0]	add_reg;
reg		[15:0]	cs_reg;
reg		ram_cs_reg;
//reg		[3:0]	add_reg;
	
//reg		[3:0]	main_state;

//reg		[7:0]	data_out_reg;
reg		[1:0]	read_reg;
reg		[1:0]	write_reg;
reg 	link_data_rd;

reg		link_data_wr;
reg		link_add;
reg		link_cs_rd;
reg		link_cs_wr;

parameter 
		
		TRUE		=1'b1,
		FALSE		=1'b0;
	
assign	data_inout=(link_data_rd&(~link_data_wr))?data_in:8'bz;
assign	data_putout=(link_data_wr&(~link_data_rd))?data_inout:8'bz;
//assign	add_wire=(link_add)?add_in:16'hffff;
assign	cs_out=(link_cs_wr|link_cs_rd)?cs_reg:16'h0000;
assign	a0_out=add_reg[0];
assign	ram_cs_out=~add_reg[15];



always@(negedge ale_in)
begin
	add_reg<=add_in;
end

always@(posedge clk_in)
begin
	if(!rst_in)
		begin
			read_reg<=2'b11;
			link_data_rd<=FALSE;
			link_cs_rd<=FALSE;
		end
	else
		begin
			if(!add_reg[15])
				begin
					read_reg[1]<=read_reg[0];
					read_reg[0]<=read_in;
					case(read_reg)
					2'b10:
						begin
							link_cs_rd<=TRUE;
						end
					2'b00:
						begin
							link_data_rd<=TRUE;
						end
					2'b01:
						begin
							link_data_rd<=FALSE;
						end
					2'b11:
						begin
							link_data_rd<=FALSE;
							link_cs_rd<=FALSE;
						end
					endcase
				end
			else
				begin
					link_data_rd<=FALSE;
					link_cs_rd<=FALSE;
				end
		end	
end

always@(posedge clk_in)
begin
	if(!rst_in)
		begin
			write_reg<=2'b11;
			link_data_wr<=FALSE;
			link_cs_wr<=FALSE;
		end
	else
		begin
			if(!add_reg[15])
				begin
					write_reg[1]<=write_reg[0];
					write_reg[0]<=write_in;
					case(write_reg)
					2'b10:
						begin
							link_data_wr<=TRUE;	
							link_cs_wr<=TRUE;
						end
					2'b00:
						begin
							//link_cs_wr<=TRUE;
							link_cs_wr<=FALSE;
						end
					2'b01:
						begin
							link_cs_wr<=FALSE;
						end
					2'b11:
						begin
							link_data_wr<=FALSE;
							link_cs_wr<=FALSE;
						end
					endcase
				end
			else
				begin
					link_data_wr<=FALSE;
					link_cs_wr<=FALSE;
				end
		end	
end

always @(add_reg[4:1])
begin
	case(add_reg[4:1])
		4'b0000:cs_reg<=16'b0000_0000_0000_0001;
		4'b0001:cs_reg<=16'b0000_0000_0000_0010;
		4'b0010:cs_reg<=16'b0000_0000_0000_0100;
		4'b0011:cs_reg<=16'b0000_0000_0000_1000;
		
		4'b0100:cs_reg<=16'b0000_0000_0001_0000;
		4'b0101:cs_reg<=16'b0000_0000_0010_0000;
		4'b0110:cs_reg<=16'b0000_0000_0100_0000;
		4'b0111:cs_reg<=16'b0000_0000_1000_0000;
		
		4'b1000:cs_reg<=16'b0000_0001_0000_0000;
		4'b1001:cs_reg<=16'b0000_0010_0000_0000;
		4'b1010:cs_reg<=16'b0000_0100_0000_0000;
		4'b1011:cs_reg<=16'b0000_1000_0000_0000;
		
		4'b1100:cs_reg<=16'b0001_0000_0000_0000;
		4'b1101:cs_reg<=16'b0010_0000_0000_0000;
		4'b1110:cs_reg<=16'b0100_0000_0000_0000;
		4'b1111:cs_reg<=16'b1000_0000_0000_0000;
	default:	cs_reg<=16'h0000;
	endcase
end
endmodule