qep_data_bus.qws

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

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ptn_Child1=Frames
ptn_Child2=ActionPoints
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ptn_Child1=StateMap
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AFC_IN_REPORT=False
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ptn_Child1=ViewFrame-0
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DocPathName=qep4.v
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ptn_Child1=StateMap
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AFC_IN_REPORT=False
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ptn_Child1=ViewFrame-0
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DocPathName=cnt_pulse.v
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ptn_Child1=StateMap
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AFC_IN_REPORT=False
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AFC_IN_REPORT=False
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AFC_IN_REPORT=False
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DocPathName=clk_gen.v
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DocPathName=d:/altera/quartus50/bin/oa_resource_table.xml
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ptn_Child1=StateMap
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AFC_CMP_AP_NAME=qep_data_bus
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ptn_Child1=StateMap
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AFC_CMP_AP_NAME=qep_data_bus
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IsActiveChildFrame=False
ptn_Child1=StateMap
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AFC_SIM_AP_NAME=qep_data_bus
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AFC_IN_REPORT=False