qep_data_bus.tan.rpt

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

; Clock Setup: 'clk_input'     ; 11.100 ns ; 40.00 MHz ( period = 25.000 ns ) ; 71.94 MHz ( period = 13.900 ns ) ; qep4:t_qep4_2|prestate[0]        ; qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] ; clk_input  ; clk_input ; 0            ;
; Clock Hold: 'clk_input'      ; 0.100 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; data_bus:t_data_bus|write_reg[1] ; data_bus:t_data_bus|link_cs_wr                                               ; clk_input  ; clk_input ; 0            ;
; Total number of failed paths ;           ;                                  ;                                  ;                                  ;                                                                              ;            ;           ; 0            ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------+------------------------------------------------------------------------------+------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                    ;
+-------------------------------------------------------+--------------------+------+-----------+-------------+
; Option                                                ; Setting            ; From ; To        ; Entity Name ;
+-------------------------------------------------------+--------------------+------+-----------+-------------+
; Device Name                                           ; EPF10K30ATC144-1   ;      ;           ;             ;
; Timing Models                                         ; Final              ;      ;           ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;           ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;           ;             ;
; Number of paths to report                             ; 200                ;      ;           ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;           ;             ;
; Use Fast Timing Models                                ; Off                ;      ;           ;             ;
; Report IO Paths Separately                            ; Off                ;      ;           ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;           ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;           ;             ;
; Cut off read during write signal paths                ; On                 ;      ;           ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;           ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;           ;             ;
; fmax Requirement                                      ; 40.0 MHz           ;      ;           ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;           ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;           ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;           ;             ;
; Enable Clock Latency                                  ; Off                ;      ;           ;             ;
; Clock Settings                                        ; clk input          ;      ; clk_input ;             ;
+-------------------------------------------------------+--------------------+------+-----------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_input       ; clk_input          ; User Pin ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; ale_in          ;                    ; User Pin ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_input'                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                          ; To                                                                            ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; 11.100 ns                               ; 71.94 MHz ( period = 13.900 ns )                    ; qep4:t_qep4_2|prestate[0]                                                     ; qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15]  ; clk_input  ; clk_input ; 25.000 ns                   ; 23.700 ns                 ; 12.600 ns               ;
; 11.200 ns                               ; 72.46 MHz ( period = 13.800 ns )                    ; qep4:t_qep4_5|lpm_counter:qep_reg_rtl_12|alt_counter_f10ke:wysi_counter|q[0]  ; qep4:t_qep4_5|lpm_counter:qep_reg_rtl_12|alt_counter_f10ke:wysi_counter|q[11] ; clk_input  ; clk_input ; 25.000 ns                   ; 23.700 ns                 ; 12.500 ns               ;