clk_4.v

来自「基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL」· Verilog 代码 · 共 48 行

module clk_4(clk_in,en_in,clk_out);
input  clk_in;
input  en_in;
output clk_out;
reg	[1:0]	clk_reg;


/*wire   clk_wire;
assign clk_wire=~clk_reg[0];
assign clk_out=clk_reg[1];
always@(posedge clk_in )
begin
	if(en_in)
		clk_reg[0]<=~clk_reg[0];
	else
		clk_reg[0]<=1'b0;
end

always@(posedge clk_wire)
begin
	if(en_in)
		clk_reg[1]<=~clk_reg[1];
	else
		clk_reg[1]<=1'b0;
end*/
wire   clk_wire;
assign clk_wire=~clk_reg[0];
assign clk_out=clk_reg[1];
always@(posedge clk_in )
begin
	if(en_in)
		clk_reg[0]<=~clk_reg[0];
	else
		clk_reg[0]<=1'b0;
	
end

always@(posedge clk_in)
begin
	if(en_in&clk_wire)
		begin
		clk_reg[1]<=~clk_reg[1];
		end
	else
		clk_reg[1]<=1'b0;
end

endmodule