test.ptf.bak

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

SYSTEM test
{
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "CYCLONE";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "1";
      do_build_sim = "1";
      hardcopy_compatible = "0";
      board_class = "";
      CLOCKS 
      {
         clk = "50000000";
      }
      hdl_language = "verilog";
      device_family_id = "CYCLONE";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "208";
      desc_column_width = "208";
      bustype_column_width = "0";
      base_column_width = "85";
      clock_column_width = "80";
      end_column_width = "85";
   }
}