qep_data_bus_debug.stp

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

<session jtag_chain="ByteBlasterMV [LPT1]" jtag_device="@1: EPF10K30A/0 (0x010300DD)" sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <global_info>
    <multi attribute="window position" size="7" value="1032,520,398,124,356,50,42"/>
    <single attribute="active instance" value="0"/>
  </global_info>
  <instance entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <position_info>
      <single attribute="active tab" value="1"/>
      <single attribute="setup vertical scroll position" value="0"/>
      <single attribute="setup horizontal scroll position" value="0"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2005/12/15 14:31:09  #0">
      <clock name="clk_input" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="256" trigger_in_enable="yes" trigger_in_node="ale_in" trigger_out_enable="no" trigger_out_pin="auto_stp_trigger_out_0"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="addr_in[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[10]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[11]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[12]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[13]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[14]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[15]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[2]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[3]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[4]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[5]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[6]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[7]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[8]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[9]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="ale_in" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="data[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data_inout[0]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[1]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[2]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[3]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[4]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[5]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[6]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[7]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="read_in" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="rst_in" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="write_in" tap_mode="classic" type="input pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="addr_in[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[10]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[11]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[12]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[13]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[14]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[15]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[2]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[3]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[4]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[5]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[6]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[7]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[8]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="addr_in[9]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="ale_in" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="data[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="data_inout[0]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[1]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[2]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[3]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[4]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[5]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[6]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="data_inout[7]" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="read_in" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="rst_in" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="write_in" tap_mode="classic" type="input pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="addr_in" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="addr_in[15]"/>
            <net is_signal_inverted="no" name="addr_in[14]"/>
            <net is_signal_inverted="no" name="addr_in[13]"/>
            <net is_signal_inverted="no" name="addr_in[12]"/>
            <net is_signal_inverted="no" name="addr_in[11]"/>
            <net is_signal_inverted="no" name="addr_in[10]"/>
            <net is_signal_inverted="no" name="addr_in[9]"/>
            <net is_signal_inverted="no" name="addr_in[8]"/>
            <net is_signal_inverted="no" name="addr_in[7]"/>
            <net is_signal_inverted="no" name="addr_in[6]"/>
            <net is_signal_inverted="no" name="addr_in[5]"/>
            <net is_signal_inverted="no" name="addr_in[4]"/>
            <net is_signal_inverted="no" name="addr_in[3]"/>
            <net is_signal_inverted="no" name="addr_in[2]"/>
            <net is_signal_inverted="no" name="addr_in[1]"/>
            <net is_signal_inverted="no" name="addr_in[0]"/>
          </bus>
          <net is_signal_inverted="no" name="ale_in"/>
          <bus is_signal_inverted="no" link="all" name="data" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="data[7]"/>
            <net is_signal_inverted="no" name="data[6]"/>
            <net is_signal_inverted="no" name="data[5]"/>
            <net is_signal_inverted="no" name="data[4]"/>
            <net is_signal_inverted="no" name="data[3]"/>
            <net is_signal_inverted="no" name="data[2]"/>
            <net is_signal_inverted="no" name="data[1]"/>
            <net is_signal_inverted="no" name="data[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="data_inout" order="msb_to_lsb" radix="hex" state="collapse" type="bidir pin">
            <net is_signal_inverted="no" name="data_inout[7]"/>
            <net is_signal_inverted="no" name="data_inout[6]"/>
            <net is_signal_inverted="no" name="data_inout[5]"/>
            <net is_signal_inverted="no" name="data_inout[4]"/>
            <net is_signal_inverted="no" name="data_inout[3]"/>
            <net is_signal_inverted="no" name="data_inout[2]"/>
            <net is_signal_inverted="no" name="data_inout[1]"/>
            <net is_signal_inverted="no" name="data_inout[0]"/>
          </bus>
          <net is_signal_inverted="no" name="read_in"/>
          <net is_signal_inverted="no" name="rst_in"/>
          <net is_signal_inverted="no" name="write_in"/>
        </data_view>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="addr_in" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="addr_in[15]"/>
            <net is_signal_inverted="no" name="addr_in[14]"/>
            <net is_signal_inverted="no" name="addr_in[13]"/>
            <net is_signal_inverted="no" name="addr_in[12]"/>
            <net is_signal_inverted="no" name="addr_in[11]"/>
            <net is_signal_inverted="no" name="addr_in[10]"/>
            <net is_signal_inverted="no" name="addr_in[9]"/>
            <net is_signal_inverted="no" name="addr_in[8]"/>
            <net is_signal_inverted="no" name="addr_in[7]"/>
            <net is_signal_inverted="no" name="addr_in[6]"/>
            <net is_signal_inverted="no" name="addr_in[5]"/>
            <net is_signal_inverted="no" name="addr_in[4]"/>
            <net is_signal_inverted="no" name="addr_in[3]"/>
            <net is_signal_inverted="no" name="addr_in[2]"/>
            <net is_signal_inverted="no" name="addr_in[1]"/>
            <net is_signal_inverted="no" name="addr_in[0]"/>
          </bus>
          <net is_signal_inverted="no" name="ale_in"/>
          <bus is_signal_inverted="no" link="all" name="data" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="data[7]"/>
            <net is_signal_inverted="no" name="data[6]"/>
            <net is_signal_inverted="no" name="data[5]"/>
            <net is_signal_inverted="no" name="data[4]"/>
            <net is_signal_inverted="no" name="data[3]"/>
            <net is_signal_inverted="no" name="data[2]"/>
            <net is_signal_inverted="no" name="data[1]"/>
            <net is_signal_inverted="no" name="data[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="data_inout" order="msb_to_lsb" radix="hex" state="collapse" type="bidir pin">
            <net is_signal_inverted="no" name="data_inout[7]"/>
            <net is_signal_inverted="no" name="data_inout[6]"/>
            <net is_signal_inverted="no" name="data_inout[5]"/>
            <net is_signal_inverted="no" name="data_inout[4]"/>
            <net is_signal_inverted="no" name="data_inout[3]"/>
            <net is_signal_inverted="no" name="data_inout[2]"/>
            <net is_signal_inverted="no" name="data_inout[1]"/>
            <net is_signal_inverted="no" name="data_inout[0]"/>
          </bus>
          <net is_signal_inverted="no" name="read_in"/>
          <net is_signal_inverted="no" name="rst_in"/>
          <net is_signal_inverted="no" name="write_in"/>
        </setup_view>
      </presentation>
      <trigger global_temp="1" name="trigger: 2005/12/15 14:31:09  #1" position="center" segment_size="1" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
        <events>
          <level enabled="yes" type="basic">
            <op_node/>
          </level>
        </events>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
</session>