io_port.v

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

module IO_Port(data_out,io,data_in,clk_in,rd_in,wr_in,rst_in,add_in);
inout	[7:0]	io;
input	rd_in,wr_in,rst_in,clk_in;
input	[7:0]	data_in;
input	[1:0]	add_in;
output	[7:0]	data_out;

reg		[7:0]	port;
reg		[7:0]	ddr;
reg		[7:0]	pin;

wire	port_link_rd;
wire	ddr_link_rd;
wire	pin_link_rd;

reg		port_link;
reg		ddr_link;
reg		pin_link;

wire	port_link_wr;
wire	ddr_link_wr;


always@(add_in)
begin
	case(add_in)
	2'b00:
		begin
			port_link=1'b1;
			ddr_link=1'b0;
			pin_link=1'b0;
		end
	2'b01:
		begin
			ddr_link=1'b1;
			port_link=1'b0;
			pin_link=1'b0;
		end
	2'b10:
		begin
			pin_link=1'b1;
			port_link=1'b0;
			ddr_link=1'b0;	
		end
	default:
		begin
			port_link=1'b0;
			ddr_link=1'b0;
			pin_link=1'b0;
		end
	endcase
end

assign	port_link_wr=(!wr_in)?port_link	:1'b0;
assign	ddr_link_wr	=(!wr_in)?ddr_link	:1'b0;

assign	port_link_rd=(!rd_in)?port_link	:1'b0;
assign	ddr_link_rd	=(!rd_in)?ddr_link	:1'b0;
assign	pin_link_rd	=(!rd_in)?pin_link	:1'b0;

assign	data_out=port_link_rd?port:8'bz;
assign	data_out=ddr_link_rd?ddr:8'bz;
assign	data_out=pin_link_rd?pin:8'bz;

assign	io[0]=ddr[0]?port[0]:1'bz;
assign	io[1]=ddr[1]?port[1]:1'bz;
assign	io[2]=ddr[2]?port[2]:1'bz;
assign	io[3]=ddr[3]?port[3]:1'bz;
assign	io[4]=ddr[4]?port[4]:1'bz;
assign	io[5]=ddr[5]?port[5]:1'bz;
assign	io[6]=ddr[6]?port[6]:1'bz;
assign	io[7]=ddr[7]?port[7]:1'bz;


always@(posedge clk_in or negedge rst_in)
begin
	if(!rst_in)
		port<=8'b0;
	else
	if(port_link_wr)
		port<=data_in;
	else
		port<=port;
end

always@(posedge clk_in or negedge rst_in)
begin
	if(!rst_in)
		ddr<=8'b0;
	else
	if(ddr_link_wr)
		ddr<=data_in;
	else
		ddr<=ddr;
end

always@(posedge clk_in)
begin
	pin<=io;
end
endmodule