📄 qep_data_bus.vwf

📁 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的
💻 VWF
📖 第 1 页 / 共 4 页
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TRANSITION_LIST("f_in[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("f_in[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("f_in[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("f_in[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("b_in[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("b_in[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("b_in[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("b_in[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("b_in[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("data_inout[0]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10525.0;
		LEVEL 0 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48975.0;
	}
}

TRANSITION_LIST("data_inout[1]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10524.2;
		LEVEL 1 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48975.8;
	}
}

TRANSITION_LIST("data_inout[2]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10523.9;
		LEVEL 0 FOR 0.1;
		LEVEL 1 FOR 2999.9;
		LEVEL Z FOR 5500.0;
		LEVEL 1 FOR 0.1;
		LEVEL 0 FOR 2499.9;
		LEVEL Z FOR 8000.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 0 FOR 0.1;
		LEVEL 1 FOR 1999.9;
		LEVEL Z FOR 48976.1;
	}
}

TRANSITION_LIST("data_inout[3]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10525.1;
		LEVEL 1 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48974.9;
	}
}

TRANSITION_LIST("data_inout[4]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10524.9;
		LEVEL 1 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48975.1;
	}
}

TRANSITION_LIST("data_inout[5]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10523.7;
		LEVEL 0 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48976.3;
	}
}

TRANSITION_LIST("data_inout[6]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10523.8;
		LEVEL 0 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48976.2;
	}
}

TRANSITION_LIST("data_inout[7]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10524.8;
		LEVEL 0 FOR 3000.0;
		LEVEL Z FOR 5500.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 8000.0;
		LEVEL 0 FOR 2500.0;
		LEVEL Z FOR 11000.0;
		LEVEL 1 FOR 2500.0;
		LEVEL Z FOR 3500.0;
		LEVEL 1 FOR 2000.0;
		LEVEL Z FOR 48975.2;
	}
}

TRANSITION_LIST("disp:t_disp|a0_reg")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|a0_reg")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|cs_reg[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|cs_reg[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("qep4:t_qep4_0|lpm_counter:qep_reg_rtl_7|alt_counter_f10ke:wysi_counter|q[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("disp:t_disp|data[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|link_data_wr")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|link_data")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|link_add")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("data_bus:t_data_bus|add_reg[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 100000.0;
	}
}

TRANSITION_LIST("clk_input")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 4000;
			LEVEL 0 FOR 12.5;
			LEVEL 1 FOR 12.5;
		}
	}
}

TRANSITION_LIST("clk_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk_input";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk_out";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "a_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "b_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clr0_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "f_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "d_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clr1_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 8;
	TREE_LEVEL = 0;
	CHILDREN = 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 8;
}

DISPLAY_LINE
{
	CHANNEL = "read_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "ale_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
💿 文件大小 1161 K
👤 上传用户 zergwyk
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#Verilog #FPGA #HDL #接口
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