qep_data_bus.qsf

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		qep_data_bus_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:42:34  NOVEMBER 16, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name VERILOG_FILE clk_gen.v
set_global_assignment -name VERILOG_FILE qep_data_bus.v
set_global_assignment -name VERILOG_FILE cnt_pulse.v
set_global_assignment -name VERILOG_FILE data_bus.v
set_global_assignment -name VERILOG_FILE disp.v
set_global_assignment -name VERILOG_FILE qep4.v
set_global_assignment -name VECTOR_WAVEFORM_FILE qep_data_bus.vwf
set_global_assignment -name SIGNALTAP_FILE qep_data_bus_debug.stp

# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS OFF
set_global_assignment -name FMAX_REQUIREMENT "40.0 MHz"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY FLEX10KA
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS ON
set_global_assignment -name IGNORE_GLOBAL_BUFFERS OFF
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS OFF
set_global_assignment -name IGNORE_LCELL_BUFFERS OFF
set_global_assignment -name IGNORE_SOFT_BUFFERS ON
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name REMOVE_DUPLICATE_LOGIC ON
set_global_assignment -name IGNORE_TRANSLATE_OFF OFF
set_global_assignment -name TOP_LEVEL_ENTITY qep_data_bus

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPF10K30ATC144-1"
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS

# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name SETUP_HOLD_DETECTION OFF
set_global_assignment -name GLITCH_DETECTION OFF
set_global_assignment -name GLITCH_INTERVAL 1ns

# Programmer Assignments
# ======================
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED OFF

# ----------------------
# start CLOCK(clk_input)

	# Timing Assignments
	# ==================
	set_global_assignment -name FMAX_REQUIREMENT "40.0 MHz" -section_id clk_input
	set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id clk_input

# end CLOCK(clk_input)
# --------------------

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# --------------------------
# start ENTITY(qep_data_bus)

	# Timing Assignments
	# ==================
	set_instance_assignment -name CLOCK_SETTINGS clk_input -to clk_input

	# Fitter Assignments
	# ==================
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to a_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to addr_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to ale_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to b_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to d_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to data_inout
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to f_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to ledout_out
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to led_out
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to ledsl_out
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to ram_cs_out
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to read_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to rst_in
	set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -from clk_in -to write_in

# end ENTITY(qep_data_bus)
# ------------------------