qep_data_bus.fit.summary

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

Flow Status : Successful - Thu Dec 15 21:16:55 2005
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : qep_data_bus
Top-level Entity Name : qep_data_bus
Family : FLEX10KA
Device : EPF10K30ATC144-1
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 904 / 1,728 ( 52 % )
Total pins : 70 / 102 ( 68 % )
Total memory bits : 0 / 12,288 ( 0 % )