play.par

用Verilog HDL 语言编写的播放梁祝的程序

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TALLENWH::  Wed Jan 11 21:18:22 2006


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 play_map.ncd play.ncd
play.pcf 


Constraints file: play.pcf

Loading device database for application Par from file "play_map.ncd".
   "play" is an NCD, version 2.38, device xc2s100, package tq144, speed -5
Loading device for application Par from file 'v100.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolved that IOB <audiof> must be placed at site P121.
Resolved that GCLKIOB <sys_CLK> must be placed at site P88.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             1 out of 92      1%
      Number of LOCed External IOBs    1 out of 1     100%

   Number of SLICEs                  114 out of 1200    9%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9898d2) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.............................
Phase 5.8 (Checksum:9a135b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file play.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 651 unrouted;       REAL time: 0 secs 

Phase 2: 584 unrouted;       REAL time: 8 secs 

Phase 3: 144 unrouted;       REAL time: 8 secs 

Phase 4: 0 unrouted;       REAL time: 9 secs 

Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 7 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|     sys_CLK_BUFGP          |  Global  |   26   |  0.094     |  0.677      |
+----------------------------+----------+--------+------------+-------------+
|          clk_6MHz          |   Local  |   10   |  0.329     |  3.621      |
+----------------------------+----------+--------+------------+-------------+
|           clk_4Hz          |   Local  |   33   |  1.877     |  3.916      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 183


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.325
   The MAXIMUM PIN DELAY IS:                               3.916
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.515

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         229         338          47          37           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 9 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file play.ncd.


PAR done.