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=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <play>. Related source file is play.v.WARNING:Xst:1872 - Variable <j> is used but never assigned. Found 1-bit register for signal <audiof>. Found 1-bit register for signal <clk_4Hz>. Found 1-bit register for signal <clk_6MHz>. Found 14-bit up counter for signal <count>. Found 24-bit up counter for signal <counter4Hz>. Found 24-bit up counter for signal <counter6MHz>. Found 14-bit register for signal <origin>. Summary: inferred 3 Counter(s). inferred 17 D-type flip-flop(s).Unit <play> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 3 14-bit up counter : 1 24-bit up counter : 2# Registers : 4 14-bit register : 1 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <origin_13> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_0> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_1> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_2> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_3> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_4> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_5> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_6> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_7> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_8> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_9> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_10> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_11> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_12> (without init value) is constant in block <play>.WARNING:Xst:1291 - FF/Latch <clk_4Hz> is unconnected in block <play>.ERROR:Xst:528 - Multi-source in Unit <play> on signal <origin<13>>Sources are: Signal <origin<12>> in Unit <play> is assigned to GND Signal <origin<11>> in Unit <play> is assigned to VCCERROR:Xst:415 - Synthesis failedCPU : 1.14 / 2.10 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 51316 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <play>.Module <play> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <play>. Related source file is play.v.WARNING:Xst:1872 - Variable <j> is used but never assigned. Found 1-bit register for signal <audiof>. Found 1-bit register for signal <clk_4Hz>. Found 1-bit register for signal <clk_6MHz>. Found 14-bit up counter for signal <count>. Found 24-bit up counter for signal <counter4Hz>. Found 24-bit up counter for signal <counter6MHz>. Found 14-bit register for signal <origin>. Summary: inferred 3 Counter(s). inferred 17 D-type flip-flop(s).Unit <play> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 3 14-bit up counter : 1 24-bit up counter : 2# Registers : 4 14-bit register : 1 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <origin_13> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_0> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_1> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_2> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_3> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_4> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_5> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_6> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_7> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_8> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_9> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_10> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_11> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_12> (without init value) is constant in block <play>.WARNING:Xst:1291 - FF/Latch <clk_4Hz> is unconnected in block <play>.ERROR:Xst:528 - Multi-source in Unit <play> on signal <origin<13>>Sources are: Signal <origin<12>> in Unit <play> is assigned to GND Signal <origin<11>> in Unit <play> is assigned to VCCERROR:Xst:415 - Synthesis failedCPU : 1.14 / 2.10 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 51316 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <play>.Module <play> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <play>. Related source file is play.v.WARNING:Xst:1872 - Variable <j> is used but never assigned. Found 1-bit register for signal <audiof>. Found 1-bit register for signal <clk_4Hz>. Found 1-bit register for signal <clk_6MHz>. Found 14-bit up counter for signal <count>. Found 24-bit up counter for signal <counter4Hz>. Found 24-bit up counter for signal <counter6MHz>. Found 14-bit register for signal <origin>. Summary: inferred 3 Counter(s). inferred 17 D-type flip-flop(s).Unit <play> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 3 14-bit up counter : 1 24-bit up counter : 2# Registers : 4 14-bit register : 1 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <origin_13> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_0> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_1> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_2> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_3> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_4> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_5> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_6> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_7> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_8> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_9> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_10> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_11> (without init value) is constant in block <play>.WARNING:Xst:1710 - FF/Latch <origin_12> (without init value) is constant in block <play>.WARNING:Xst:1291 - FF/Latch <clk_4Hz> is unconnected in block <play>.ERROR:Xst:528 - Multi-source in Unit <play> on signal <origin<13>>Sources are: Signal <origin<12>> in Unit <play> is assigned to GND Signal <origin<11>> in Unit <play> is assigned to VCCERROR:Xst:415 - Synthesis failedCPU : 1.19 / 2.14 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 51316 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling source file "play.v"tdtfi(verilog) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <play>.Module <play> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================INFO:Xst:1304 - Contents of register <origin> in unit <play> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <play>. Related source file is play.v.WARNING:Xst:1872 - Variable <j> is used but never assigned. Found 1-bit register for signal <audiof>. Found 1-bit register for signal <clk_4Hz>. Found 1-bit register for signal <clk_6MHz>. Found 14-bit up counter for signal <count>. Found 24-bit up counter for signal <counter4Hz>. Found 24-bit up counter for signal <counter6MHz>. Summary: inferred 3 Counter(s). inferred 3 D-type flip-flop(s).Unit <play> synthesized.⌨️ 快捷键说明
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