__projnav.log

用Verilog HDL 语言编写的播放梁祝的程序

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<0>>
Sources are: 
   Output signal of FDR instance <counter_ren_0>
   Output signal of FDR instance <counter_0>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<5>>
Sources are: 
   Output signal of FDR instance <counter_ren_5>
   Output signal of FDR instance <counter_5>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<4>>
Sources are: 
   Output signal of FDR instance <counter_ren_4>
   Output signal of FDR instance <counter_4>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<3>>
Sources are: 
   Output signal of FDR instance <counter_ren_3>
   Output signal of FDR instance <counter_3>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<2>>
Sources are: 
   Output signal of FDR instance <counter_ren_2>
   Output signal of FDR instance <counter_2>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<1>>
Sources are: 
   Output signal of FDR instance <counter_ren_1>
   Output signal of FDR instance <counter_1>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<12>>
Sources are: 
   Output signal of FDR instance <counter_ren_12>
   Output signal of FDR instance <counter_12>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<13>>
Sources are: 
   Output signal of FDR instance <counter_ren_13>
   Output signal of FDR instance <counter_13>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <origin<13>>
Sources are: 
   Signal <origin<12>> in Unit <play> is assigned to GND
   Signal <origin<11>> in Unit <play> is assigned to VCC

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<19>>
Sources are: 
   Output signal of FDR instance <counter_ren_19>
   Output signal of FDR instance <counter_19>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<14>>
Sources are: 
   Output signal of FDR instance <counter_ren_14>
   Output signal of FDR instance <counter_14>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<18>>
Sources are: 
   Output signal of FDR instance <counter_ren_18>
   Output signal of FDR instance <counter_18>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<23>>
Sources are: 
   Output signal of FDR instance <counter_ren_23>
   Output signal of FDR instance <counter_23>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<17>>
Sources are: 
   Output signal of FDR instance <counter_ren_17>
   Output signal of FDR instance <counter_17>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<22>>
Sources are: 
   Output signal of FDR instance <counter_ren_22>
   Output signal of FDR instance <counter_22>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<16>>
Sources are: 
   Output signal of FDR instance <counter_ren_16>
   Output signal of FDR instance <counter_16>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<21>>
Sources are: 
   Output signal of FDR instance <counter_ren_21>
   Output signal of FDR instance <counter_21>
ERROR:Xst:415 - Synthesis failed
CPU : 1.62 / 2.58 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 51316 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "play.v"
Module <play> compiled
No errors in compilation
Analysis of file <play.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <play>.
Module <play> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <play>.
    Related source file is play.v.
WARNING:Xst:1872 - Variable <j> is used but never assigned.
    Found 1-bit register for signal <audiof>.
    Found 1-bit register for signal <clk_4Hz>.
    Found 1-bit register for signal <clk_6MHz>.
    Found 14-bit up counter for signal <count>.
    Found 24-bit up counter for signal <counter>.
    Found 14-bit register for signal <origin>.
    Summary:
	inferred   3 Counter(s).
	inferred  17 D-type flip-flop(s).
Unit <play> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 3
 14-bit up counter                 : 1
 24-bit up counter                 : 2
# Registers                        : 4
 14-bit register                   : 1
 1-bit register                    : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <origin_13> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_0> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_1> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_2> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_3> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_4> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_5> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_6> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_7> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_8> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_9> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_10> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_11> (without init value) is constant in block <play>.
WARNING:Xst:1710 - FF/Latch  <origin_12> (without init value) is constant in block <play>.
WARNING:Xst:1291 - FF/Latch <clk_4Hz> is unconnected in block <play>.

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<15>>
Sources are: 
   Output signal of FDR instance <counter_ren_15>
   Output signal of FDR instance <counter_15>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<10>>
Sources are: 
   Output signal of FDR instance <counter_ren_10>
   Output signal of FDR instance <counter_10>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<9>>
Sources are: 
   Output signal of FDR instance <counter_ren_9>
   Output signal of FDR instance <counter_9>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<20>>
Sources are: 
   Output signal of FDR instance <counter_ren_20>
   Output signal of FDR instance <counter_20>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<8>>
Sources are: 
   Output signal of FDR instance <counter_ren_8>
   Output signal of FDR instance <counter_8>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<7>>
Sources are: 
   Output signal of FDR instance <counter_ren_7>
   Output signal of FDR instance <counter_7>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<6>>
Sources are: 
   Output signal of FDR instance <counter_ren_6>
   Output signal of FDR instance <counter_6>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<11>>
Sources are: 
   Output signal of FDR instance <counter_ren_11>
   Output signal of FDR instance <counter_11>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<0>>
Sources are: 
   Output signal of FDR instance <counter_ren_0>
   Output signal of FDR instance <counter_0>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<5>>
Sources are: 
   Output signal of FDR instance <counter_ren_5>
   Output signal of FDR instance <counter_5>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<4>>
Sources are: 
   Output signal of FDR instance <counter_ren_4>
   Output signal of FDR instance <counter_4>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<3>>
Sources are: 
   Output signal of FDR instance <counter_ren_3>
   Output signal of FDR instance <counter_3>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<2>>
Sources are: 
   Output signal of FDR instance <counter_ren_2>
   Output signal of FDR instance <counter_2>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<1>>
Sources are: 
   Output signal of FDR instance <counter_ren_1>
   Output signal of FDR instance <counter_1>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<12>>
Sources are: 
   Output signal of FDR instance <counter_ren_12>
   Output signal of FDR instance <counter_12>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<13>>
Sources are: 
   Output signal of FDR instance <counter_ren_13>
   Output signal of FDR instance <counter_13>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <origin<13>>
Sources are: 
   Signal <origin<12>> in Unit <play> is assigned to GND
   Signal <origin<11>> in Unit <play> is assigned to VCC

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<19>>
Sources are: 
   Output signal of FDR instance <counter_ren_19>
   Output signal of FDR instance <counter_19>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<14>>
Sources are: 
   Output signal of FDR instance <counter_ren_14>
   Output signal of FDR instance <counter_14>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<18>>
Sources are: 
   Output signal of FDR instance <counter_ren_18>
   Output signal of FDR instance <counter_18>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<23>>
Sources are: 
   Output signal of FDR instance <counter_ren_23>
   Output signal of FDR instance <counter_23>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<17>>
Sources are: 
   Output signal of FDR instance <counter_ren_17>
   Output signal of FDR instance <counter_17>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<22>>
Sources are: 
   Output signal of FDR instance <counter_ren_22>
   Output signal of FDR instance <counter_22>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<16>>
Sources are: 
   Output signal of FDR instance <counter_ren_16>
   Output signal of FDR instance <counter_16>

ERROR:Xst:528 - Multi-source in Unit <play> on signal <counter<21>>
Sources are: 
   Output signal of FDR instance <counter_ren_21>
   Output signal of FDR instance <counter_21>
ERROR:Xst:415 - Synthesis failed
CPU : 1.67 / 2.62 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 51316 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "play.v"
Module <play> compiled
No errors in compilation
Analysis of file <play.prj> succeeded.
 
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "play.v"
tdtfi(verilog) completed successfully.


Release 6.3i - spl2sym G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "play.v"
Module <play> compiled
No errors in compilation
Analysis of file <play.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <play>.
Module <play> is correct for synthesis.