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Project Navigator Auto-Make Log File-------------------------------------
Compiling source file "divf.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling source file "divf.v"tdtfi(verilog) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledNo errors in compilationAnalysis of file <divf.prj> succeeded. Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Compiling source file "divf.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"ERROR:HDLCompilers:28 - play.v line 20 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 30 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 31 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 32 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 33 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 34 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 35 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 36 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 42 'j' has not been declaredERROR:HDLCompilers:28 - play.v line 42 'j' has not been declaredERROR:HDLCompilers:28 - play.v line 42 'j' has not been declaredERROR:HDLCompilers:28 - play.v line 42 'j' has not been declaredERROR:HDLCompilers:26 - play.v line 44 unexpected token: '='ERROR:HDLCompilers:28 - play.v line 45 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 46 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 47 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 48 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 49 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 50 'origin' has not been declaredERROR:HDLCompilers:28 - play.v line 51 'origin' has not been declaredModule <play> compiledAnalysis of file <play.prj> failed.--> Total memory usage is 48244 kilobytesERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"ERROR:HDLCompilers:26 - play.v line 44 unexpected token: '='Module <play> compiledAnalysis of file <play.prj> failed.--> Total memory usage is 48244 kilobytesERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling source file "play.v"tdtfi(verilog) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================WARNING:HDLCompilers:259 - play.v line 13 Connection to input port 'sysf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 13 Connection to input port 'divf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 14 Connection to input port 'sysf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 14 Connection to input port 'divf' does not match port sizeAnalyzing top module <play>.Module <play> is correct for synthesis. Analyzing module <divf>.ERROR:Xst:870 - divf.v line 19: Can not simplify operator DIV. Found 1 error(s). Aborting synthesis.--> Total memory usage is 50292 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================WARNING:HDLCompilers:259 - play.v line 13 Connection to input port 'sysf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 13 Connection to input port 'divf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 14 Connection to input port 'sysf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 14 Connection to input port 'divf' does not match port sizeAnalyzing top module <play>.Module <play> is correct for synthesis. Analyzing module <divf>.ERROR:Xst:870 - divf.v line 19: Can not simplify operator DIV. Found 1 error(s). Aborting synthesis.--> Total memory usage is 50292 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling source file "divf.v"Module <divf> compiledCompiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================WARNING:HDLCompilers:259 - play.v line 13 Connection to input port 'sysf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 13 Connection to input port 'divf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 14 Connection to input port 'sysf' does not match port sizeWARNING:HDLCompilers:259 - play.v line 14 Connection to input port 'divf' does not match port sizeAnalyzing top module <play>.Module <play> is correct for synthesis. Analyzing module <divf>.ERROR:Xst:870 - divf.v line 19: Can not simplify operator DIV. Found 1 error(s). Aborting synthesis.--> Total memory usage is 50292 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================ERROR:HDLCompilers:247 - play.v line 19 Reference to scalar wire 'clk_6MHz' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - play.v line 19 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - play.v line 32 Reference to scalar wire 'clk_4Hz' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - play.v line 32 Illegal left hand side of blocking assignment--> Total memory usage is 50292 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "play.v"Module <play> compiledNo errors in compilationAnalysis of file <play.prj> succeeded. Completed process "Check Syntax".
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