divf.v.bak

用Verilog HDL 语言编写的播放梁祝的程序

module divf(divf_CLK,CLK,CLR,sysf,divf);

input CLK,CLR;
input[31:0] sysf,divf;
output divf_CLK;

reg[31:0] count; //max 2~32 
reg divf_CLK;

always @(posedge CLK or posedge CLR)
begin
   if(CLR)
   begin
       count=0;
       divf_CLK=0;
   end
   else
   begin
	   if(count==sysf/(divf*2))
	   begin
		   count=0;
		   divf_CLK=~divf_CLK;
	   end
	   else
	   begin
		   count=count+1;
	   end
	end
end

endmodule