signal.v

正交信号源的单片机和cpld源码

/*-----------------------------------------------*-
  File for  signal sourse
-*-----------------------------------------------*/
module signal(reset,clk,step_value,phase_addr1,phase_addr2);
input clk;
input reset;
//input cpld_syn;
//input cpld_En;
input [7:0]step_value;
  
output [8:0]phase_addr1;
output [8:0]phase_addr2

reg [23:0]step_value_buf;
reg [8:0]phase_addr1;
reg [8:0]phase_addr2;
reg [24:0]phase_adder;
always@(posedge clk or negedge reset)
  begin
    if(!reset)
       begin
          step_value_buf<=24'b0000_0000_0000_0000_0000_0000;
         // state<=state0;
       end
    else 
       begin
          step_value_buf[7:0]<=step_value;
        end
  end 
always@(posedge clk or negedge reset)
  begin
    if(!reset)
        begin
          phase_adder<=25'b0000_0000_0000_0000_0000_0000;
        end
    else 
        begin
           phase_adder<=phase_adder+step_value_buf;
          if((phase_addr1>=9'b101101000)|(phase_addr2>=9'b101101000))
             begin
             phase_adder[24:16]<=9'b0_0000_0000;
             end
           phase_addr1<=phase_adder[24:16]; 
           phase_addr2<=phase_adder[24:16];
        end 
  end
endmodule